Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

High-Density Small Form-Factor Package with Polygon-Shaped Capacitor Based on Silicon Technology

Abstract: This paper suggests a unique silicon capacitor shape to provide a very competitive package form-factor with limited height condition. To locate a discrete capacitor on the BGA side of package, some solder balls must be depopulated to secure capacitor mounting space. Also to implement silicon based multi terminal capacitor with fine pitch bumped format, a conventional capillary underfill dispensing keep out zone should be considered. The removed solder balls may affect the system PDN with the decreased power connection or overall X-Y dimension expansion with the increased SOC functionality. To find an optimized shape and size against various BGA arrangement option, it is very important to have a successful product solution. A comparative study of various design concept of normal rectangular and polygonal shape of capacitor on BGA side with respect to area usage efficiency, maximum ball usage, and power integrity performance enhancement for high-density small form-factor package is described in this paper. The number of depopulated solder balls will be increased according to the use of multiple capacitors with rectangular shape. But, it can be optimized with one big polygonal shape and multiterminal of silicon capacitor. Interposer POP package for mobile device will be used as a target package type and the latest structure of substrate and ball pitch will be used for the study to reflect a realistic scenario.

The electromagnetic compatibility analysis based on a navigation system

Abstract: In this paper, the electromagnetic compatibility based on a navigation system has been studied. The EMC problems occurring in the engineering application has been focused on and the signal integrity and power integrity of the system has been simplified. In order to reduce the influence of SI, PI and EMI, a newly design scheme has been put forward, which corresponds to the acceptable simulation result. Finally, it has been proved that the system could work well through EMC test. Above all, the signal integrity analysis, power integrity analysis and EMI analysis are done with the hyperlynx software.

Analysis of multilayer interconnects distributed energy-per-bit and power integrity with Kron-Branin formalism

Abstract: With the increase of the operation speed and the miniaturization, the power consumption assessment of multilayer printed circuit board (PCB) becomes a crucial task during the design phase. More accurate power integrity (PI) analysis is necessary for the complex multilayer PCB. An unfamiliar modelling of static and dynamic power distributed through a four-layer interconnect structure is introduced in this paper. The modelling concept is based on the Kron-Branin (KB) formalism. The different steps of the proposed KB modelling are described with the consideration of the RLC equivalent model and its equivalent graph topology. The KB model efficiency is validated with the static and dynamic powers distributed through the multilayer structure by considering 20 ns duration and 0.5 ns rise/fall time a pulse signal. The computed energy-per-bit and average powers are compared with simulations from a commercial 3D EM computational tool.

Package design methodology in consideration with signal integrity, power integrity and electromagnetic immunity

Abstract: A design concept and methodology for package with consideration on signal integrity, power integrity and electromagnetic immunity is proposed in this paper. Each part of the package such as bonding wire, via or bump has a significant influence on the performance of entire chip-package-board system, and these effects to signal, power integrity prosperities are discussed based on the numerical analysis method and SPICE-like simulator. Furthermore, a novel design for filter in package is proposed for enhancing immunity of integrated circuits. Finally, the methodology for design optimization can be achieved based on the analysis results.