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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings Article
Xavier Lecoq, Stephane Cosmo1, Prem Bacle1, Corinne Devey1, Olivier Bayet1, Laurent Schwarz1 
01 Sep 2013
TL;DR: In this paper, the IC-package-PCBASP system co-design process is analyzed based on the implementation of a digital baseband, highlighting the value of early Electro-Magnetic (EM) and electrical simulations (including Power Integrity / Signal Integrity [PI/SI]), and illustrates the links between the system codesign and substrate technology / assembly / manufacturing constraints.
Abstract: When it comes to developing an advanced flip-chip Package-on-Package (PoP) for a mobile application, challenges are daunting: what are the keys to insure that the IC-package-PCB system is optimized with respect to the physical, the electrical and the thermal constraints while meeting the cost, the technology, the integration and the low power targets? The combined physical and electrical system co-design process enables us to reach high-performance and quality results. From the early prototyping stage to the final implementation, the physical co-design must follow electrical design rules, as well as constraints coming from substrate technology, manufacturing and assembly. As the electrical rules are application, frequency and technology dependent, early electro-magnetic (EM) and electrical simulations are always required to define the first guidelines, including floorplan and routing recommendations on the IC, package and PCB. Even if the flow can be either PCB-driven or IC-driven, the target should always be the global optimization from a system and customer point of view. As the level of integration is always very high, it is essential to have quickly a global view on the sensibility of high-speed interfaces and demanding IP's. Then the next steps are to obtain sufficient design margin and to properly balance the routing resources. Based on the implementation of a digital baseband, this paper shows the important aspects of the IC-package-PCB co-design process, highlights the value of early Electro-Magnetic (EM) and electrical simulations (including Power Integrity / Signal Integrity [PI/SI]), and illustrates the links between the system co-design and substrate technology / assembly / manufacturing constraints.

2 citations

Journal ArticleDOI
TL;DR: In this paper , a new efficient unconditionally stable time-domain modeling algorithm based on the weighted Laguerre polynomial finite-difference timedomain (WLP-FDTD) method is proposed for noise analysis of complex three-dimensional (3-D) power distribution networks (PDNs) including interposers, chips, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors.
Abstract: In this article, a new efficient unconditionally stable time-domain modeling algorithm based on the weighted Laguerre polynomial finite-difference time-domain (WLP-FDTD) method is proposed for noise analysis of complex three-dimensional (3-D) power distribution networks (PDNs) including interposers, chips, through-silicon via (TSV) arrays, bumps, and metal–insulator–metal (MIM) capacitors. Combined with weighted Laguerre polynomials (WLPs) as basis functions and Galerkin’s testing procedure, the time variables in the differential equations can be eliminated. Complex structures composed of different ON-chip/interposer PDNs and TSV/bump arrays are modeled and assembled. Subsequently, the differential equations of the 3-D PDN are derived and solved based on WLP-FDTD. Thus, the proposed algorithm can obtain the transient response and analyze noise coupling in a complex 3-D integrated circuit (IC) for the first time. Meanwhile, based on three reasonable test cases, the algorithm can save at least 99.3% and 77.0% computational time compared with the conventional FDTD and SPICE methods, respectively. In addition, the simultaneous switching noise (SSN) in a popular 3-D PDN structure is modeled, calculated, and optimized. An optimal decoupling capacitor selection scheme is discussed, and efficient SSN suppression is achieved.

2 citations

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties, and the simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions.
Abstract: Power integrity design is a critical issue for advanced CMOS LSIs which operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be designed as low as possible in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation. In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

2 citations

Patent
11 Jan 2019
TL;DR: In this article, a method for constructing a small power integrity risk index of a power supply station based on big data, belonging to the data processing field, is presented, which includes: building asmall and micro power-integrity risk evaluation data center based on business information system, building small and micro-power integrity risk evaluation index, based on the actual data, evaluatingthe small micro-Power integrity risk indicators, extracting actual data to evaluate and screen the indicators, determining the index weight, calculating the small micro power -integrity index, carrying out the small-power
Abstract: The invention provides a method for constructing a small power integrity risk index of a power supply station based on big data, belonging to the data processing field. The method includes: building asmall and micro power integrity risk evaluation data center based on business information system, building small and micro power integrity risk evaluation index, based on the actual data, evaluatingthe small micro-power integrity risk indicators, extracting the actual data to evaluate and screen the indicators, determining the index weight, calculating the small micro-power integrity risk index,carrying out the small micro-power integrity risk rating, and carrying out the trend analysis and early warning of the small micro-power integrity risk index based on the actual data. By using the rich business data accumulated in existing business information systems, current data is rated by constructing an evaluation system, so corresponding measures are taken according to the rating results to improve the small power risk management and information level of power supply substation, effectively identify the small power integrity risk and enhance the risk prevention and control capacity.

2 citations

Patent
22 Sep 2015
TL;DR: In this article, the authors compare metal fill locations with an average least resistance path (LRP) for a cell and then fill the location with either power or ground tiles based on the comparison.
Abstract: In the physical design of an integrated circuit, comparing metal fill locations with an average least resistance path (LRP) for a cell and then filling the location with either power or ground tiles based on the comparison. For each metal layer, all of the metal fill locations are determined and nearby metal fills, i.e., those within a predetermined radius of a located metal fill are connected. A Design Rule Check (DRC) is performed to ensure that connected metal fills meet design specifications, for example, that connected metal fills are not too close to a signal line. The metal fill method improves the power integrity of the design.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852