Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Behavioral Modeling of Pre-emphasis Drivers Including Power Supply Noise Using Neural Networks

Abstract: This paper addresses the nonlinear behavioral modeling of pre-emphasis drivers including power supply noise. The proposed multiple-port model relies on the use of power-aware weighting functions that control the driver’s output stage to model the pre-emphasis behavior with non-ideal power supply accurately. The weighting functions are implemented using feed-forward neural networks (FFNNs), and the dynamic memory characteristics of driver’s ports are captured using recurrent neural networks (RNNs). Practical industrial driver example demonstrates that the proposed modeling method offers good accuracy, flexibility and significant simulation speed-up to facilitate signal integrity and power integrity analysis without compromising intellectual property (IP).

Maintaining System Signal and Power Integrity Characteristics as Part of a Module Cost-Reduction Exercise

Abstract: This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical properties and characteristics of the ceramic and organic package designs were not absolutely identical, it was necessary to perform electrical equivalency analyses at the system level.

Research on SiP Signal Integrity Based on Ansys SIwave in Wearable Medical Systems

Abstract: One of the main challenge for wearable medical systems is how to integrate more functional ICs in a very small space. As a kind of new packaging and system integration technology, SiP (System in Package) simplifies the system design and complies with the requirements of device miniaturization with multi-component integration. However, high layout and routing density in SiP substrate tend to cause SI (Signal Integrity) and PI (Power Integrity) issues. This paper introduces the main reasons and improvement measures for signal and power integrity issues in SiP designs. Based on ANSYS SIwave simulation platform, the simulation process of major parameters for signal and power integrity and related optimization methods are discussed in the design process of SiP.

High bandwidth low latency chip to chip interconnects using high performance MLC glass ceramic POWER4/sup R/ MCM

Abstract: This paper describes a high performance multi-layer ceramic (MLC) four chip glass-ceramic multi-chip module (MCM) that achieves very high bandwidth and low latency performance by incorporating unique design approaches and features. These include leveraging an I/O ring pattern arrangement using the fine line capability of IBM's High Performance Glass Ceramic (HPGC) and the capability to use 30+ wiring layers with isolating reference planes. The attendant signal integrity is assured by providing a tailored reference structure to control impedance and cross-talk coupling while maintaining the chip C4 I/O area density without requiring thin-films or degrading the power integrity.

Top-layer inductance extraction for the pre-layout power integrity using the physics-based model size reduction (PMSR) method

Abstract: Proper power integrity analysis is required for printed circuit board (PCB) power distribution network (PDN) design. Developing a simple physics-based equivalent circuit model for critical structures is essential for understanding the physics of the system and for intelligent designs. In this paper, a physics-based model size reduction (PMSR) method is applied to get the equivalent circuit model for the above-ground geometries. The extracted physics-based models are also based on PEEC, and can be used in analyzing the structure in its parts. By applying PMSR method, a physics-based equivalent circuit model can be proposed and this circuit model is related to the geometric features of the design. In this way, PMSR method can provide an intuitive guideline in designing PCB and reducing above inductances, therefore, a low-ripple DC voltage can be delivered through PDN. Taking advantage of PEEC and PMSR methods, the top-layer inductances of three different geometries (the shared via design, the doublet design and the shared pad design) are calculated and the physics-based circuit models are obtained, respectively.