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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings Article
07 Nov 2013
TL;DR: In this article, an equation-based method combing field equations with circuit solver is proposed for calculating electromagnetic susceptibility on printed circuit board (PCB), which can be simplified to a voltage source and a current source, and then substituted into commercial software to calculate the impact of incident electromagnetic waves on traces on PCB.
Abstract: An equation-based method combing field equations with circuit solver is proposed for calculating electromagnetic susceptibility (EMS) on printed circuit board (PCB). These equations can be simplified to a voltage source and a current source, and then substituted into commercial software to calculate the impact of incident electromagnetic waves on traces on PCB. This paper compares the results calculated by equivalent sources with those done by method of moments (MoMs). Good agreement between those two methods. Finally, a commercial software, SPEED 2000, is used to combine with the equivalent sources to calculate the problems of signal integrity (SI) and power integrity (PI) under the influence of incident electromagnetic waves.

2 citations

Proceedings ArticleDOI
01 Oct 2008
TL;DR: In this article, a power distribution system (PDS) design on IC package is discussed and studied, and the simulation approach will cover complete Signal Integrity (SI) and Power Integrity (PI) analysis to quantify the electrical performance.
Abstract: The high performance window-BGA for a high speed Synchronous Dynamic Random Access Memory (SDRAM) has been designed. In this paper, power distribution system (PDS) design on IC package is discussed and studied. A appropriate PDS design will provide not only the stable power supply but also the superior current return path for signal channels. The simulation approach will cover complete Signal Integrity (SI) and Power Integrity (PI) analysis to quantify the electrical performance. The parasitical parameters of IC package including resistance, inductance and capacitance are extracted to check low frequency performance, and S-parameters are performed to observe the broad bandwidth response to ensure sufficient low transmission loss through entire operation frequency range. The PDS behavior in both frequency and time domain are characterized to make sure the PDS performance. Finally, eye diagram are analyzed to inspect overall electrical performance.

2 citations

Proceedings ArticleDOI
26 May 2015
TL;DR: In this article, the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations is investigated, and it is shown that an insertion loss of <0.55 dB/mm can be achieved assuming dense interconnection.
Abstract: Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are valued by measurements. Our measurements show that microstrip lines with <0.3 dB/mm insertion loss at 30 GHz can be achieved with a typical polymer based interposer process. In contrast to other work we extend the microstrip line model with pads on both ends to form a complete interconnection. Our investigations show that an insertion loss of <0.55 dB/mm can be achieved assuming dense interconnections. We investigate the impact of technological variations during the manufacturing process of a silicon interposer. This is important to ensure electrical functionality (signal and power integrity) of the system in mass production. The results on technology variations during the manufacturing process of an interposer show that variations of 20 % in trace width and trace height are changing the characteristic impedance of the line, but do not significantly affect the signal integrity of sufficiently long lines. In contrast, variations of 20 % in polymer height and polymer permittivity in the redistribution layer have more influence on signal integrity of sufficiently long interposer interconnections.

2 citations

Proceedings ArticleDOI
09 Jul 2007
TL;DR: In this article, a robust co-analysis approach for signal integrity, power integrity, and electromagnetic compatibility is successfully established and demonstrated through the investigation of several signal referencing configurations in double data rate (DDR) memory systems.
Abstract: A robust co-analysis approach for signal integrity, power integrity, and electromagnetic compatibility is successfully established and demonstrated through the investigation of several signal referencing configurations in double data rate (DDR) memory systems. The characterization of power noise coupling into signal channels for two configurations is presented. In addition, a new metric that quantifies the entire signaling system combining simultaneous switching noise and crosstalk is detailed. Finally, the radiated emissions from the power planes in the signalling system are reduced through the proper placement of decoupling capacitors.

2 citations

01 Jan 2015
TL;DR: In this article, a physics-based model size reduction (PMSR) method is used to reduce the equivalent inductance of a decoupling capacitor connection to achieve low-ripple DC voltage from a Voltage Regulator Module (VRM) to an IC.
Abstract: Power Distribution Network (PDN) for Printed Circuit Board (PCB) design requires proper power integrity analysis. In order to deliver a low-ripple DC voltage from a Voltage Regulator Module (VRM) to an Integrated Circuit (IC), a certain target input impedance should be achieved. Developing simple physics-based equivalent circuit models are essential for understanding how a system works and making crucial design decisions. In this work, the input impedance of a decoupling capacitor due to traces, pads and via discontinuities are investigated using the Physics-based Model Size Reduction (PMSR) method. Various decoupling capacitor connection methods are compared and design guidelines are provided for reducing the equivalent inductance to meet target impedance requirements. It is shown that a shared pad having 179 pH equivalent Labove loop inductance is a better design choice as compared to a doublet or shared via design with 218 pH and 406 pH Labove loop inductance respectively. The second part of this thesis relates to BroadR-Reach® technology, a point-topoint Ethernet Physical Layer (PHY) standard, which is used in automotive applications. This technology allows full-duplex communication between two devices over a single, Unshielded Twisted wire Pair (UTP) cable. Here, alien crosstalk in a 6 UTP bundle is investigated for meeting electromagnetic compatibility requirements. The performance of Alien Near-End and Far-End Crosstalk of two different UTPs with and without an inline Circular Plastic Connector (CPC) are compared to standard limits. An inline connector in the middle of a 15 m 6 UTP cable bundle, with a 25 cm untwisted region fails the PSANEXT standard limit by 4 dB at 100 MHz, while the same bundle without the connector passes the standard by a margin of 8 dB at 100 MHz.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852