Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Power, signal integrity for 25-Gbps, 40-dB compensation signal conditioner for backplane architecture

Abstract: A 25-Gbps/lane 40-dB compensation signal conditioner was developed. The target architecture was a long channel backplane with two connectors that have large reflections due to impedance discontinuities. Jitters originating from the power integrity (PI) and signal integrity (SI) are critical for a bit error rate (BER) less than 1E-12 because 1 unit interval (UI) is small at high speed. A technique for frequency dependent decap was designed to reduce the PI jitter. Also, a non-linear equalization for the reflections technique was designed to reduce the SI jitter. Our test chip can achieve 2.5 ps PI and 10.0 ps SI jitter, respectively. The sum of the PI and SI jitter can be reduced to less than 0.32 UI. Finally, our test chip can achieve a BER of less than 1E-12 for a 40-dB backplane with two connector traces.

Improving Power Integrity by Using Magnetodielectric Absorbers Along the Perimeters of Printed Circuit Boards

Abstract: Maintaining low and smooth impedance over a wide range of frequency is one of the main issues in designing high-speed digital systems or mixed signal integrated circuits Cavity resonances of a printed circuit board coupled with discontinuous return current paths, series inductance of the power distribution network, and parasitic inductance make potentials at power/ground planes unstable One possible solution to improve power integrity and electromagnetic interference is to utilize a magnetodielectric absorber on the perimeter of the board A mode-matching method and an impedance boundary condition are employed to obtain a computationally inexpensive model of the system A contour plot of transfer impedance versus normalized surface impedance is introduced to provide useful information for determining the most suitable absorber Numerical and measurement results are discussed The results from the proposed modeling agree with those from the measurement and the simulation The selected absorber effectively reduces selfimpedance and transfer impedance at resonant frequencies, but resonances are not completely eliminated at low frequencies due to the low loss of the absorber

Decoupling-capacitor allocation problem solved by genetic algorithm

Abstract: Decoupling capacitors allocated closely to LSIs work well in order to increase PI (power integrity) in PDNs (power distribution networks). In the higher frequency range more than 5 GHz, however, we have to allocate the decoupling capacitors in the whole power-plane as the allocation target area instead of the vicinity of the LSI because of the power-voltage standing waves shorter than the power plane size. This allocation problem becomes a combinatorial explosion problem, which has no deterministic solving approach. We apply the GA to this problem, and also propose a novel chromosome suits to the power plain structure. In the simulation experiment, GA successfully obtains an effective solution that decrease the strongest impedance less than half of that in the conventional allocation.

Signal and Power Integrity Design Methodology for High-Performance Flight Computing Systems

Abstract: Computing capabilities of space systems have increased onboard performance by orders of magnitude with the use of radiation-tolerant field-programmable gate arrays (FPGA) and processors. The incorporation of signal and power integrity analysis with printed circuit board (PCB) design in reliable computing architectures for space systems has become critical to enable future mission capabilities. Developers launch high-performance processors into a breadth of orbits and missions, running varying applications that create challenges for designing reliable computing hardware. Specifically, for these designs, academic and industry research has focused on component radiation performance, fault mitigation, and reliable architectures. However, other design parameters including electromagnetic interference (EMI), PCB stackup, signal integrity (SI), voltage regulator module (VRM) design, and power distribution network (PDN) are often deprioritized or disregarded as the design matures. Since these characteristics are becoming more significant in high-performance processor designs, this research presents a hardware design and analysis methodology for high-performance, space-computing systems that focuses on a holistic design approach and PDN reliability. While these challenges exist across all space hardware, the reduced PCB dimensions imposed by SmallSats and CubeSats introduce additional hurdles, specifically to VRM and decoupling design. By examining the relationship between the PDN and radiation performance, an analytical relationship is developed that incorporates Total Ionizing Dose and Single-Event Transients to ensure reliability throughout the mission duration. The presented design methodology is applied to the SpaceCube v3.0 Mini, an FPGA-based on-board science data processing system developed at NASA Goddard Space Flight Center.