Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Device physics aware 3D electromagnetic simulation of Through-Silicon-Vias in system modeling

Abstract: Three dimensional integrated circuits (3DICs) are generating considerable interest as a way to increase speed and density while reducing power and form factor. Among the different forms of 3D integration, the use of Through Silicon Vias (TSV) with micro-bumps in a passive interposer is a popular choice in applications ranging from wide IO memory to heterogeneous integration. Current compact modeling strategy aims at modeling TSVs with circuit elements whose values are typically computed from analytical expressions. This technique therefore does not capture system level coupling effects like TSV-Redistribution Layer (RDL) coupling. This paper presents a device physics aware 3D electromagnetic modeling of TSV structures with the capability of modeling full systems including coupling between conventional package-board layers and TSV embedded passive interposers, towards accurate signal and power integrity analysis and design.

Closed-form small signal model of a buck controller including power transmission lines

Abstract: The input-to-output transfer function of a buck converter is investigated including power transmission line parameters, accounting for printed circuit board (PCB) parasitics. A closed-form relation is developed for the transfer function to be used in small-signal analysis. Also, the effect of power transmission lines is demonstrated on control-to-output transfer function of the converter.

The Design and Simulation a Subsystem under Electromagnetic Interference to Enhance the System's Performance

Abstract: High-speed digital boards should be able to have integrity validation credentials within the framework of the specified criteria. In order to improve the simulation results, the package designer should consider the management of the radiation level at the board, which will reduce the time and cost of implementing the design and manufacturing process. In order to achieve this goal, the integrity (signal, power, heat, and data) is of great importance. With the modeling and analysis of the transmission line in one of the near paths of the clock to reduce electromagnetic interference, good results can be obtained from the correct operation of the board. Due to the nature and location of the components and the complexity of the input signals, it also increases the reliability of components and the tolerance of electromagnetic interactions, to evaluate the performance of the subsystem under the influence of radiation, various practical tests on the range and results was recorded.

Design of the PCB embedded active IC structure for ultra-thin wearable application with low-RFI

Abstract: The ultra-thin design is essentially required for mobile and wearable applications, while the multiple operations are needed to be integrated in tiny space of the product. For achieving ultra-thin design and low radio-frequency interference (RFI) characteristics, the PCB embedded active IC structure was proposed in previous studies. However, there were limitations for fabricating the structure: one is difficulty to test, the other is high cost of the process, and the other is still exposure to RFI. In this paper, we propose the structure that can be fabricated by using normal PCB process with an anisotropic conductive film (ACF) bonding. The structure, which we propose, can overcome the limitations of the previous PCB embedded active IC structure. Among limitations, RFI could be effectively reduced by noise field reduction of radiation and conduction. The shielding effectiveness is key factor for reducing radiated field coupling, and signal integrity (SI) and power integrity (PI) factors, such as crosstalk and PDN mode resonance is critical factor for reducing conducted field coupling.

Probe Card Design with Signal and Power Integrity for Wafer-Level Application Processor Test in LPDDR Channel

Abstract: In this paper, a vertical probe card design for wafer-level mobile application processor (AP) chip test is proposed under LPDDR4 channel specifications. The probe card consists of a probe head and a multi-layer ceramic (MLC) board, and it is designed to have signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps of speed under 1.1 V of supply voltage. We proposed insertion of additional ground cobra-shaped needles insertion in the probe head to reduce crosstalk noise and secure return current path. In the far-end crosstalk (FEXT) noise simulation and eye-diagram simulation, FEXT noise in the proposed probe head is suppressed 20 dB at 1.6 GHz, and the eye-open size is increased from 17.9 % to 83.3 % at 1.6 Gbps of speed. Measurements are also conducted and well correlated with the simulation results. In MLC board design, over 500 number of 1 uF decoupling capacitors are implemented on the top layer and the bottom side of the board to lower power distribution network (PDN) impedance. In addition, some power planes for LPDDR memory power supplies are repositioned to upper layers of the board. The PDN impedance curves of the memory power domains are lowered by nearly 20 dB at frequencies above the GHz range. To validate the proposed methods, the original and the revised probe card are compared in the frequency-and time-domain simulations. S-parameters of the probe head are extracted from 3-D EM simulation, and those of the MLC board are extracted from SIwave simulation. For exact eye-diagram simulations, eye-mask information and various conditions of LPDDR4 channel are referred to JEDEC standard.