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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Journal ArticleDOI
TL;DR: The paper explores the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and proposes a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off.
Abstract: This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.

24 citations

Journal ArticleDOI
TL;DR: Based on the electrical properties of fabricated transmission lines, the improved Root-Omega method applied to cases with smooth and rough conductors is validated using simulations in this article, and the error sensitivity is significantly reduced by the proposed improvements.
Abstract: Electrical properties of dielectric substrate are critical in designing high-speed products in terms of signal and power integrity. It is important to accurately characterize the dielectric properties to avoid overestimating or underestimating in the design. This paper proposes the improved “Root-Omega” method for extracting dielectric properties from fabricated multilayer printed circuit boards. Based on the electrical properties of fabricated transmission lines, the improved “Root-Omega” method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original “Root-Omega” procedure and the error sensitivity is significantly reduced by the proposed improvements.

24 citations

Proceedings ArticleDOI
Joong-Ho Kim1, Woopoung Kim1, Dan Oh1, R. Schmitt1, J. Feng1, Chuck Yuan1, Lei Luo1, John Wilson1 
21 Nov 2007
TL;DR: The impact of SSO on high performance graphic memory systems (GDDR3/4) is studied using a systematic approach considering both signal and power integrity simultaneously, and a data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise.
Abstract: Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

23 citations

Proceedings ArticleDOI
01 Jan 2007
TL;DR: The experimental results demonstrate that the force-directed floorplanning technique can effectively suppress supply noise experienced by modules, reduce the total number of supply-noise margin violations, and achieve a floor-plan with considerably lower IR drop, as compared to a wire-length driven floorplan.
Abstract: This paper proposes noise-direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constraints have led microprocessor designers to incorporate aggressive power saving techniques such as clock-gating, that place a significant burden on the power delivery network. While the application of extensive clock-gating can effectively reduce power consumption, unfortunately, it can also induce large inductive noise (di/dt), resulting in signal integrity and reliability issues. To combat these problems, processors are usually designed for the worst-case current consumption scenario using adequate supply voltage and decoupling capacitances. To tackle high-frequency inductive noise and potential IR drops, we propose a novel design methodology that integrates microarchitectural profiling feedback into the floorplanning process. We present two microarchitectural metrics to quantify the noise susceptibility of a module:self weighting and correlation weighting. By using these metrics in a force-directed floorplanning algorithm to assign power pin affinity to modules, we can quickly converge to a design for average-case current consumption. By designing for the average-case and employing dynamic di/dt control for the worst-case, we can ensure that a chip is noise-tolerant without exceeding decap budget constraints. Our observations showed that certain functional modules in a processor exhibit consistent and highly correlated switching activity, that can be used to guide module placement distance from power pins. The experimental results demonstrate that the force-directed floorplanning technique can effectively suppress supply noise experienced by modules, reduce the total number of supply-noise margin violations, and achieve a floor-plan with considerably lower IR drop, as compared to a wire-length driven floorplan.

23 citations

Proceedings ArticleDOI
07 Jun 2004
TL;DR: The methods for the fast analysis of the P/G networks at the floorplanning stage are presented and the analyzer is integrated into a commercial tool to develop a power integrity (IR drop) driven design methodology.
Abstract: As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the voltage (IR) drop become a serious problem in modern VLSI design. Traditional power/ground (P/G) network analysis methods are typically very computationally expensive and thus not feasible to be integrated into floorplanning. To make the integration of the P/G analysis with floorplanning feasible, we need a very efficient, yet sufficiently accurate analysis method. In this paper, we present the methods for the fast analysis of the P/G networks at the floorplanning stage and integrate our analyzer into a commercial tool to develop a power integrity (IR drop) driven design methodology. Experimental results based on three real-world circuit designs show that our P/G network analyzer is accurate enough and very efficient.

23 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852