Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Mesh conforming electro-thermal co-analysis with application to PCB power integrity

Abstract: Modern design of Printed Circuit Boards (PCB) applies electric IR drop analysis in order to optimize the supply voltage margins for the ICs mounted on the board. The IR drop however is affected by the heat generation in the PCB due to the temperature dependency of the material conductivities. Both the electric power dissipation inside the IC's and the Joule losses in the copper contribute to the heat generation. The electric problem is coupled with the thermal problem and is to be solved in a co-analysis setup to obtain thermal aware IR drop values. This paper presents an electro-thermal co-analysis technology targeting PCB designers responsible for Power Integrity (PI). We deploy a finite element discretization technique to solve the coupled electro-thermal steady-state equations simultaneously. Our solution combines H(div) Whitney face elements with mesh conformity. That is, the mesh used in the electric domain is reused in the thermal domain preserving all geometrical details in both domains. The exchange of electric data (power loss) and thermal data (temperature) at the mesh level speeds up the design process and increases the accuracy of the simulations. The electro-thermal co-simulation technique is validated using a via test board and applied for a real DDR4 board to demonstrate the significance of thermal aware IR drop.

Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV

Abstract: The selection of a suitable bump shape is critical to the performance of a 3D packaging system. The most widely used bump shape (cylindrical) is facing significant reliability issues, including coefficient of thermal expansion (CTE) mismatch, stress and power loss. Bump with a tapered shape have procured a lot of attention recently because of their low volume fraction and coupling capacitance, which can significantly minimize stress and crosstalk related delay. In order to quantify the effective CTE and stress of different solder structures the bump/underfill composite assembly is quantitatively studied using 3D unit-cell technique, which takes evenly distributed bump in the underfill. The temperature-dependent effective CTE of the evenly distributed bump incorporating the volume fraction can be used for the analysis of the stress issues. Additionally, for the analysis of the power loss, the analytical π based impedance network is proposed. The model was successfully verified by EM simulation under the different frequency range. Furthermore, a distinctive electromagnetic (EM) based model is used to analyze the NEXT (Near end) and FEXT (Far end) crosstalk delay using coupled bump arrangement at 32 nm technology. Using Computer Simulation Microwave Studio (CST MWS) industry-standard EM simulations tool, the crosstalk induced delay is obtained upto 20 GHz operating frequencies for different bump architectures i.e. cylindrical, spherical and tapered. Considering a tapered bump, a substantial improvement in NEXT, FEXT, and CTE at 32 nm technology is observed as 3.39%, 4.02%, 7.03%, 8.08% 11.88%, and 40.18% respectively compared to the spherical and cylindrical bump.

Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

Abstract: An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6 $$\%$$ and the conversation of the simulation time is about 99.9 $$\%$$ compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.

A novel design methodology for reducing simultaneous switching noise evaluated by a differential-ibis structure ¤

Abstract: Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

A 56 Gbps I/O Interface Design with Exact Power Source Simulation: Total I/O Circuit Design with over 28 GHz from Driver to Receiver Device Models

Abstract: For over 20 GHz board level I/O interface circuits, the most serious problem is its high power consumption due to arrange adequate signal forming (pre-emphasis, adaptive equalizer, etc.) and timing adjust circuits that generally require 200 mW/lane for 28-56 Gbps interface. To reduce the power consumption, binary signal (Non Return to the Zero, NRZ) transmission system is fitted to eliminate easily above arrangements. Implementation with FR-4 printed circuit board (PCB) would be an only solution to tackle the problem of production cost of the transmission system. It is well known there are many technical challenges to realize over 200 mm transmission line for signal integrity even with 10 Gbps. With our simulation based analyses, we found that many studies have discussed signal integrity (SI) and power integrity (PI) issues only the range from MHz to 10 GHz of frequency. So it is necessary to consider the transmission parameters of the entire frequency range from direct current (DC) for high-speed I/O circuits especially in transistor level, because MOS devices need constant voltage for the switching operation. In this study, total I/O interface circuit, from CMOS driver through package interconnection to CMOS receiver, is examined mainly by simulation basis for 28 to 56 Gbps signaling. Three types of design were chosen as high speed differential driver / receiver device models, and the transmission characteristics were compared for the SI. One model is developed with TSMC's 65 nm IP, and other models are with 32 nm and 20 nm fin structure models of the Arizona State University's Predictive Technology Model (PTM). The PI parameters for the 40 mm and 200 mm wiring on PCBs, package with capacitors, and chip wiring including on-chip capacitor were studied to reach as possible as ideal voltage source by S-parameter simulation from DC to 100 GHz. We achieved the successful results of the target performance of 56 Gbps in some considered configuration. And the power consumption of our design can be achieved as low as 35 mW on this rate. The most significant aspect to realize our circuit design is the co-design among all I/O circuit parameters. The most effective parameters for our design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration. We made the configuration of the PDF (PDN) at resonance frequency as high as 6.5 GHz. The driver device models examined in this study exhibited no explicit differences in performance up to 56 Gbps.