Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Power distribution network analysis in Deep Submicron Designs

Abstract: Described an importance, complexity and limitations of power distribution network analysis in Deep Submicron Designs. Proposed a three-stage way of Power Integrity (PI) checks to account for standard PI tools' capacity limitation of on-die short and high time resolution and die + package long and low time resolution PI analysis.

Enhanced Mpilog macromodels for Signal and Power Integrity Simulations

Abstract: Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The...

Experimental study of supply voltage stability during ESD

Abstract: On-chip power supply integrity may be compromised during a power-on ESD event, e.g. system-level ESD. Experimental data are provided to show that the supply integrity is a function of the rail clamp gain, its speed of response to ESD, and the amount of on-chip supply decoupling capacitance. It is also demonstrated that just a few nH of package inductance can cause the on-chip supply to briefly collapse, regardless of the rail clamp response speed.

Design of on-chip linear voltage regulator module and measurement of power distribution network noise fluctuation at high-speed output buffer

Abstract: By applying on-chip linear VRM, PDN inductance is greatly decreased and PDN resonance peak disappears, which is usually generated by PCB/PKG inductance and on-chip capacitance. To confirm, we design an application circuits which have on-chip linear voltage regulator module (VRM) with aggressor and victim buffer. We validate the advantages of on-chip linear VRM by measuring fabricated chip in this research. Moreover, we show PDN self-impedance at output buffer by simulation with designed PCB's S-parameter, and eye-diagram power fluctuation up to 1 Gbps.

Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning

Abstract: Large-scale systems-on-a-chips (SoCs) have stringent power requirements to ensure adequate supply of power to on-die devices and prevent catastrophic timing violations. Heterogeneous voltage regulation (HVR) leveraging a combination of on-chip and off-chip voltage regulators has been advocated for ensuring power integrity with maximum efficiency. However, unavoidable process and temperature variations have not been considered in prior HVR work. In this paper, we present an in-depth evaluation of the impacts of process and temperature variations on HVR. Furthermore, we propose a systemic solution to incorporate variation awareness into the HVR system control policy to add a further improvement of up to 4.28% in system power efficiency with minimal hardware overhead.