Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

PI(Power Integrity)를 이용한 EMI 개선

Abstract: It is difficult to solve PCB(Printed Circuit Board) Noise problem. Because Electronic circuit system operates very high frequency. Resonance analysis of PCB layout by PI(Power Integrity) Simulation method visualizes distribution of Switching noise between VDD and GND. By using de-cap, we reduce impedance and solve the EMI problems.

Improvement of Power and Signal Integrity through Layer Assignment in High-Speed Memory Systems

Abstract: In high-speed systems, large switching current drawn from power supply seriously degrades the system performance. This paper discloses a signal integrity (SI) issue related to power integrity (PI). A high-speed memory subsystem is used to evaluate the impact of switching current on SI using eye diagrams. Several test cases are studied to clarify the signal susceptibility from the voltage variation of power due to switching current. Full-wave and circuit simulations are used to validate the hypothesis of noise immunity.

Integrated circuit having bump pads and semiconductor package including the same

Abstract: Disclosed are an integrated circuit including bump pads and a semiconductor package including the integrated circuit. The integrated circuit according to an exemplary embodiment of the present disclosure includes a plurality of bond pads which are arranged in rows inside the integrated circuit, and a plurality of bump pads which are electrically connected to the plurality of bond pads. The plurality of bump pads are arranged in at least two rows in parallel with the rows of the bond pads based on signal integrity and power integrity. Accordingly, the present invention can improve the integrity of power and a signal moving through the pads.

Improvement of Noise Characteristics by Analyzing Power Integrity and Signal Integrity Design for Satellite On-board Electronics

Abstract: As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.

Buffer/flip-flop block planning for power-integrity-driven floorplanning

Abstract: As the technology scaled down, it is known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of very effective and useful techniques to improve the interconnect performance. In order to find better places for buffers to be inserted, the buffer insertion stage during floorplanning usually clusters buffers in a region, which may cause additional IR-drop violation. On the other hand, in complex digital system with relatively large die areas operating at very high frequencies, many global signals traveling across the chip need several clock cycles to reach their destinations, thus requiring the adoption of pipelined interconnects. Together with the buffer stations/blocks, the increasing number of flip-flops will cause further voltage drop violation. In this paper, we propose a methodology to pipeline interconnect during the floorplan stage and consider the IR-drop during the planning of buffers and flip-flops at the same time. The experimental results show that our method can get a low system latency with power integrity preservation in 90nm technology node.