Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Analysis and Reduction of Coupling Noise in Embedded Wideband Data Acquisition System

Abstract: This paper investigates the coupling noise in embedded wideband data acquisition system that has low signal integrity and power integrity performance. The study firstly designs a set of experiments to characterize and quantify the source and the coupling of the interference signals, such as nearfield measurement and power noise measurement in frequency domain. Secondly, with the help of the full-wave simulation, the paper reveals the inter-layer coupling paths. Finally, based on the results of measurement and simulation analysis, the PCB layout of the embedded system is modified and the performance of the signal integrity is improved. Moreover, the measurement results show that most of the coupling noise is reduced significantly.

A novel decoupling capacitor for power integrity of quad flat nonlead (QFN) package

Abstract: This paper describes the progressions for power and signal integrity issues on quad flat non-lead (QFN) package. A novel decoupling capacitor is achieved by modifying the footprint of QFN package. The modified footprint is connected to printed circuit board (PCB) power plane and coated the solder mask above. A large decoupling capacitor between power and ground is achieved by thin film solder mask and large size of die pad, which parallel to and decrease the input impedance of power delivery network (PDN) without parasitic effects at low frequency. After 2 GHz, adding more vias can decrease and shift the high impedance caused by equivalent inductance of via to high frequency. This novel decoupling capacitor is fully compatible with PCB process and significantly decreasing the high impedance of PDN.

Perils of power prediction in early power-integrity analysis

Abstract: Early power integrity and peak power analyses for multi-million gate system on chip (SoC) in advanced technology nodes pose significant methodology definition and implementation challenges. Typically in a SoC, processors and other high performance IPs are dominant contributors to peak power and power integrity issues. To get an early look ahead of potential power integrity issues and to estimate peak di/dt issues in the SoC, it is always desired to analyze potential issues early and address before a silicon failure. This paper presents an overview of implementation challenges faced in RTL based power for predictive power analysis and analyzing peak di/dt issues ahead of time in the context of TI C66x DSP core based multicore SoC.

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM

Abstract: In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.