Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Dual Referencing Simulation Approach on High Speed Interconnects USB3.2 (10Gbps)

Abstract: Despite our computing technology and platform design are trending toward higher speeds for better performance, on the contrary, the printed circuit board (PCB) form factor needs to scale smaller and thinner to allow for bigger battery for battery life improvement. Due to this, layout design with dual referenced (SIG-PWR or GND-SIG-PWR) stack-up could not be avoided at all due to the limitation that we have on routing spaces or routing layers. In this paper, signal and power integrity (SIPI) co-simulation approach on USB3.2 with dual referencing is described and discussed. The co-sim approach is carried out using Advanced Design System (ADS) tool in time-domain where the power noise is directly injected to the power plane and its noise coupling impact on USB3.2 eye opening at the receiver end is then observed.

Platform PI-PD co-design and validation for power efficient HSIO interfaces

Abstract: An efficient and effective methodology for platform power delivery and power integrity (PD-PI) co-analysis and design optimization has been developed, for investigating high yield loss, to support SoC validation. Both frequency and time domain results have demonstrated good correlation between simulation and lab measurement. Consequently it enabled quick verifying the root cause and optimizing work-around power delivery fixing solutions, and further provided optimal PD configuration scheme to key customers for their platform design.

Improvement of power integrity with Die-Attached STO thin film capacitors

Abstract: This paper demonstrates that our Die-Attached STO thin film decoupling capacitor is effective for reduction of the resonant power supply noise of LSIs. Shmoo plots shows improvement of operable frequency and power supply voltage reduction, as results of the improved power integrity realized by our STO thin film capacitors.

The Collaborative Design for the Package of High - speed Interface Chip

Abstract: In order to meet people's demand for multi-function and miniaturization of electronic products, the integration degree of electronic products is constantly improving and the speed is getting faster and faster. The research takes an actual DDR3 controller package design as the background. And the chip adopts advanced packaging collaborative design, including die-package-PCB collaboration design and design-simulation collaboration design. Packaging is evaluated in terms of electrical integrity, thermal mechanical properties, manufacturability, testability and so on during package.

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis

Abstract: As the VLSI technology goes into the nanometer era, the device sizes and supply voltages are continually decreased. The smaller supply voltage reduces the power dissipation but also decreases the noise margin of devices. Therefore, the power integrity problem has become one of the critical issues that limit the design performance (Blakiewicz & Chrzaniwska-Jeske, 2007; kawa, 2008 & Michael et al., 2008). Most of the power supply noises (PSNs) come from two primary sources. One is the IR-drop and the other is the simultaneous switching noise (SSN). Figure 1(a) illustrates a typical RLC model for power supply networks, which is the combination of on-chip power grids and off-chip power pins. The IR-drop is a power supply noise when the supply current goes through those non-zero resistors and results in a I·R voltage drop. The simultaneous switching noise (SSN) is the supply noise which happens when large instantaneous current goes through those non-zero inductors on power networks and generates a L·(di/dt) voltage drop. When the supply voltage is reduced , the noise margin of devices also decreases as shown in Fig.1(b). It may induce worse performance because the driving capability of devices becomes week due to smaller supply voltage. If serious power supply noise occurs, the logic level may be changed, which causes function error in the circuit. The worst situation is the electronmigration (EM) effects. Supply wires are shorten or broken because a large current travels through the small supply wires. Therefore, the power supply noise analysis is reguired at design stages to evaluate the effects caused by power supply noise.