Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Novel LC resonant clocking for 3D IC using TSV-inductor and capacitor

Abstract: At sub-14nm regime, large area overhead induced by on-chip capacitor and inductor is a major concern to ensure power integrity or enable on-chip applications. To overcome this issue, a novel 3D Through-Silicon-Via (TSV) based capacitor is investigated in this work, which may achieve both high density and high performance. The capacitor simulated in this work alleviates the depletion effect adding doping region around the TSV so that the capacitor can maintain its maximum value within operation voltage range. Moreover, the equivalent serial resistance of the proposed capacitor is reduced through doping and distributed grounded contact technology. An LC resonant clock is also simulated in this work, by replacing conventional capacitor and inductor to TSV based structures, it may achieve a 16.3x capacitor area reduction and 2.2x inductor area reduction while the performance stays almost the same.

Design and implementation of electromagnetic diagnostics electronics in SST-1 Tokamak

Abstract: Electromagnetic (EM) Diagnostics is one of the most important diagnostics tools to measure the key parameters such as the current, position, loop voltage and Magneto Hydro Dynamic MHD activities of the plasma in SST1 (Steady State Tokamak), designed for long pulse (1000 s) operation. A frontend electronic scheme for conditioning the dynamic (10mV to 2V) range of signals over the entire time span is designed that incorporates features such as remote parameter setting, self-test and calibration, saturation detection, storing of default values and system health monitoring and also adopts methodologies to address issues related to noise, signal and power integrity and low channel density. The entire scheme is implemented in a 3U size chassis. 28 numbers of channels of AD215 isolation amplifiers are integrated in 7-modules with 4-channels/module. Each module is designed to operate in different modes like attenuation, amplification, calibration, dc error check, self-test and standby. These modes of operation can be selected using a LabVIEW based GUI from a remote PC. A TMS320F38335 based controller module is designed for this purpose and is being integrated in the chassis. The controllers of all the chassis of EM diagnostics are interconnected through CAN network and connected to a remote PC through Ethernet. A discussion on the design, implementation and results of this electronic scheme is presented in this paper.

Power-Aware Timing Analysis for High-Speed Memory Interface

Abstract: As the speed of advanced memory products exceeding multi-GHz range, signal integrity (SI) and power integrity (PI) analysis becomes imperative to ensure robust timing performance. This paper will explore a couple of methodologies of on-chip power delivery network (PDN) modeling, and provide a flexible and accurate simulation flow for power-aware timing analysis. Power supply induced jitter (PSIJ) will be examined for 8Gbits LPDDR5 mobile products with a data rate up to 6400Mbps using 1y-nm DRAM process. Package and SoC (system-on-chip) co-simulation can be included as well to extend the PI analysis into system level.

Modeling, characterization and simulation of on-chip power delivery networks and temperature profile on multi-core microprocessors

Abstract: Reliable on-chip power delivery is a challenging design task for sub-100nm and below VLSI technologies as voltage IR drops become more and more pronounced. This situation gets worse as technology continues to scale down. And efficient verification of power integrity becomes critical for design closure. In addition, the increasing process-induced variability makes it even worse for reliable power delivery networks. The process induced variations manifest themselves at different levels (wafer level, die-level and within a die) and they are caused by different sources (lithograph, materials, aging, etc.). In this dissertation, for power delivery networks without considering process variations, we propose an efficient simulation approach, called ETBR (Extended Truncated Balanced Realization), which uses MOR (Model Order Reduction) to speed up the simulation. To make ETBR more accuracy, we further introduce an error control mechanism into it. For power delivery networks with considering process variations, we propose varETBR (variational Extended Truncated Balanced Realization), a reduced Monte-Carlo simulation approach, which can handle a large number of variables and different variation distributions. To further speedup the MOR process used in the fast simulation, a hierarchical Krylov subspace projection based MOR approach, hiePrimor, is proposed.Besides the on-chip power delivery, excessive on-chip temperature has also become a first-tier design constraint as CMOS technology scales into the nanometer region. The exponential increase of power density of the high-performance microprocessors leads to the rapid rising of the average chip temperature. Higher temperature has significant adverse impacts on chip package cost, performance, and reliability. Multi-core techniques provide a viable solution to temperature/power problems. However, designing thermal efficient multi-core microprocessors remains a challenging problem as the temperature in each core can be dramatically different and the resulting large temperature gradients can produce mechanical stress and degrade the chip reliability. In this dissertation, we investigate a new architecture-level dynamic thermal characterization problem from a behavioral modeling perspective to address the emerging thermal related analysis and optimization problems for high-performance multi-core microprocessor design. We propose a new approach, called ThermPOF, to build the thermal behavioral models from the measured or simulated thermal and power information at the architecture level. And then we extend ThermPOF into ParThermPOF, a parameterized thermal behavioral modeling approach that can handle different parameters in multi-core microprocessor design and optimization.

Signal Integrity Analysis for Dual-Stripline Design

Abstract: In today’s PCB design, dual-stripline is gaining more popular as it provides more density for signal routing of little PCB thickness therefore thinner products. However, it is becoming more important to keep track of signal and power integrity issues brought by the convenience of dual-stripline structure. It is well known dual-stripline crosstalk would cause severe problems for signals, in addition, for power rails as well. It is important to predict the problem beforehands with simulation and avoid the troubleshooting and debugging. In this work, the investigation of dual-stripline design is studied to figure out signal-to-signal coupling. A comprehensive solution is provided for this convenient structure in both simulation and measurement manners.