Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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26 May 2015
TL;DR: In this article, the authors present a fast and efficient method based on unit MCTL calibration for a predictive modeling of different PDNs sizes, which can reduce design iterations due to signal and power integrity issues, even if layout is not yet designed.
Abstract: Due to the high speed and system miniaturization trends in circuit design, predictive modeling of Power Distribution Network (PDN) in modern multilayered packages and boards becomes more and more important. To reduce design iterations due to signal and power integrity issues, the PDN model needs to be anticipated at early design stage, even if layout is not yet designed. Typical package PDNs consists of multiple layers of Power/Ground planes hence we can model it with a mesh of Multi-Conductor Transmission Lines (MCTLs). This paper presents a fast and efficient method based on unit MCTL calibration for a predictive modeling of different PDNs sizes.
1 citations
TL;DR: This paper proposes a design approach for each problem of waveform distortion problem and power-supply drop problem, both of which are based on the genetic algorithm, and obtained improvement ratios of more than double compared with the both conventional designs for SI and PI degradations.
Abstract: As operation frequencies of the printed circuit boards (PCBs) increase in keeping with VLSI frequencies in the GHz domain, two independent serious problems occur in the PCB design. One is waveform distortion problem, or signal integrity (SI) degradation problem, in PCB traces. And the other is power-supply drop problem, or power integrity (PI) degradation problem, in PCB power planes. Those problems are barely able to be overcome on case-by-case empirical designs conventionally. In this paper we newly propose a design approach for each problem, both of which are based on the genetic algorithm. And we obtained improvement ratios of more than double compared with the both conventional designs for SI and PI degradations, respectively.
1 citations
21 Mar 2005
TL;DR: This work sheds light on a new chip-package codesign paradigm and all the technologies necessary to enable it, and discusses parameterized reduced order models accounting for all high frequency SI effects in the package that can be reliably and automatically extracted by field solvers.
Abstract: Summary form only given. Signal integrity (SI) and power integrity are forecast to be paramount issues for future chip and package designs. Larger numbers of IOs, higher frequencies, and tighter noise margins necessitate the merging of the design paradigms for chip IO and package. We shed light on a new chip-package codesign paradigm and all the technologies necessary to enable it. We first discuss parameterized reduced order models accounting for all high frequency SI effects in the package that can be reliably and automatically extracted by field solvers. We then introduce package-aware chip IO planning and placement, which is the key to chip-packaging codesign. Finally, we cover detailed power and signal integrity modeling and optimization in package.
1 citations
01 Dec 2018
TL;DR: The methodology presented here is based on different sections of power and ground net pairs and is supported by extensive simulation results.
Abstract: High-Speed Multi-Chip HTCC Packages for Avionics require careful considerations early in the design cycle to obtain the optimum electrical performance. Some design goals can be achieved with simple stackup or layout modifications, but others require a detailed analysis using electromagnetic field solvers [1]–[3]. This paper proposes a design methodology and various guidelines to meet the optimum electrical performance in terms of Power Integrity. The methodology presented here is based on different sections of power and ground net pairs and is supported by extensive simulation results.
1 citations
07 May 2017
TL;DR: In this paper, a measurement-based large signal model that supports AC, DC Transient, Harmonic Balance, and EM simulation is presented, which supports voltage mode and current mode controlled regulators in continuous (CCM) and discontinuous conduction (DCM) modes.
Abstract: The voltage regulator module (VRM) forms the foundation of the power distribution network. The most efficient method of optimizing the VRM design is simulation. While there are accurate small signal models for Peak Current Mode (PCM) control, today's simulations require large signal response as well as small signal response. It is also desirable to evaluate time domain response and support continuous and discontinuous conduction modes simultaneously, as might occur from a large dynamic current change. This paper presents a measurement-based large signal model that supports AC, DC Transient, Harmonic Balance, and EM simulation. The unified model supports voltage mode and current mode controlled regulators in continuous (CCM) and discontinuous conduction (DCM) modes. The proposed model simulates very quickly and can be created from just a few simple measurements.
1 citations