Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Electromagnetic Band Gap structure for cut off of low frequency noise in 3-D printed circuit board

Abstract: This paper describes the design of mushroom EBG (Electromagnetic Band Gap) structure within slit defected on power supply plane in order to control PI (power integrity) for realizing high-density multi-stacked printed circuit board Generally, EBG structure is not suitable to block the low frequency noise around 1GHz in the printed circuit board, because EBG structure requires large area to cutoff low frequency noise In this paper, new type of mushroom EBG structure, which has slit defect on power supply plane, to increase inductance for EBG function was proposed By applying the new mushroom EBG structure of small patch size 10mm × 10mm × 3 pieces in the 09 mm thickness printed circuit board, we realized -40dB isolation at stop band frequency 094GHz~125GHz Consequentially, the multi-stacked printed circuit board thickness could be reduced to 81% of using conventional mushroom EBG structure

WWAN solution of NB display interface through silicon-package-board co-design

Abstract: In addition to wireless local area network (WLAN), a wireless wide area network (WWAN) provides an alternative manner for people to connect to the internet with much larger coverage, achieved using cellular tower technology. For a typical notebook (NB) design with built-in WWAN feature, the WWAN antennas are usually located in the top or two sides of the display panel and thus susceptible to the conductive/radiative coupling of digital display signal. This paper takes advantage of the silicon-package-board (SPB) signal integrity/power integrity (SI/PI) co-simulation methodology to find out the root cause of WWAN problems as well as provide chip- and system-level solutions with real measurement validation.

Integral power net integrity analysis of a packaged u-Controller system including the u-Controller on-chip power net distribution

Abstract: In this paper an application of Integral Analysis Techniques is demonstrated for determining the effect of large simultaneously switching IC Circuit Groups (internal IC-Circuits and I/O's ) on their Power Integrity (PI) and I/O-Signal Integrity (I/O-SI) behavior. The analysis includes the complex Packaging (CP+PCB). A large u-Controller and its wire-bonded Chip-Package(CP) plus its Test-PCB have been used for our study, which is in this paper focused on the analysis of Conducted Power Emission Noise in Frequency- and Time-Domain (FD, TD). The FD-power analysis results are shown in comparison with related Spectrum Analyzer measurements. The methodology can analogously be applied to conducted I/O Signal Noise. The achieved short CPU run times and the ease-of- use are underlined.

Cost-effective optimization of serial link system for Signal Integrity and Power Integrity

Abstract: Signal Integrity (SI) and Power Integrity (PI) are the most inportant characteristics for system level design, simulation and analysis of high speed systems. In this paper, HSLINK system is optimized for better SI and PI. Linear models for eye amplitude and jitter are derived by Design of Experiments (DOE). Cost effective solution strategy is also presented using linear models obtained.

A novel design for evaluating simultaneous switching noise within an enhanced IBIS model

Abstract: Simultaneous switching noise (SSN) is a major cause of power integrity (PI) degradation that causes circuits to become unstable and experience errors As modern ICs operate at higher speeds with higher density and lower voltages, SSN has become a serious issue that must be addressed to ensure system stability during the short rise- and fall-times of the logic transient states Most traditional designs have generally used decoupling capacitors to reduce SSN As these capacitors become equivalent series inductances when the system operates at high frequencies, such a technique works against reducing SSN Therefore, we propose a methodology called the enhanced IBIS model that effectively alleviates the problem of SSN using an evaluation based on the enhanced I/O buffer information specification (IBIS) model with decoupling capacitors and a high-frequency low-impendence circuit In this study, we showed that SSN from 452 mV, 290 mV, 163 mV, and 301 mV, of IBIS, traditional decoupling capacitors, IBIS with a high-frequency low-impendence circuit, and HP Simulation Program with Integrated Circuit Emphasis (HSPICE) methodologies, respectively, was effectively reduced by 121 mV of our enhanced IBIS mode as measured by the peak-to-peak value That is, our new method reduces noise by more than 732%, 583%, 257%, and 598% compared to other four methodologies, respectively