Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Abstract: This article describes how 3-D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning (ML), can be implemented within a 3-D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core concept to address issues such as system scalability, where we connect multiple 3-D XPoint arrays, and power integrity, where we analyze the parasitic effects of metal lines on noise margins. To assure power integrity within the 3-D XPoint array during this implementation, we carefully analyze the parasitic effects of metal lines on the accuracy of the implementations. We quantify the impact of parasitics on limiting the size and configuration of a 3-D XPoint array, and estimate the maximum acceptable size of a 3-D XPoint subarray.

A Novel Absorptive Power Delivery Network for Power Noise Mitigation

Abstract: In this article, for the first time, a power delivery network (PDN) noise absorber is applied to the power system and verified based on a power trace system. Among all the existing absorptive circuits, a low-pass reflectionless circuit is chosen as our PDN noise absorber due to its broadband characteristic. Since the speed of the signal becomes higher and higher nowadays, a millimeter distance of a power trace with the traditional reflective PDN noise suppression devices, such as decoupling capacitors (de-caps), may provide serious standing wave on it and seriously affect the system. The proposed PDN noise absorber, on the other hand, can absorb the PDN noises so that the standing wave on the power trace can be prevented. This makes power trace systems more stable and avoids significant power noises at some locations. A prototype using a PDN noise absorber was fabricated. The power integrity performance of this prototype was compared with two other cases, power trace only and power trace with a de-cap. Compared with the de-cap case at the designed frequency 750 MHz, a PDN noise absorber can reduce 40% maximum voltage ripple. On the other hand, noise coupling between the digital and radio frequency circuits has also been demonstrated and compared for those three different PDNs. It shows a 3.7-dB decrease in gain fluctuation for the PDN with power noise absorber compared with the de-cap case. According to these results, no matter from power integrity or noise coupling suppression viewpoint, PDN noise absorber can be a good candidate to make the power system more stable.

Pinout Optimization for 10 Gbps+ Serial Link Routing

Abstract: Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost. At high frequencies, such as >10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a si...

Power supply chip, printed circuit board and manufacturing method of printed circuit board

Abstract: The invention provides a power supply chip, a printed circuit board and a manufacturing method of the printed circuit board, and solves the problems that the partial pressure of inductance in a return circuit is too large, the increased impedance causes the partial pressure to be increased, then the voltage, distributed by the power supply, to others chips is decreased, and thus power integrity is poor. The power supply chip comprises a power supply pin and an earthing pin, wherein a capacitor burying material with a set characteristic parameter is added between the power supply pin and the earthing pin, and used for decreasing inductance of a connecting circuit on which the power supply chip is arranged. Through the addition of the capacitor burying material, the connected outer wires are reduced, then the return circuit area of the power supply chip and a decoupling capacitor is reduced, and thus the inductance of the connecting circuit on which the power supply chip is arranged is decreased.