Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

A parallel framework for transient power integrity analysis

Abstract: This paper presents an efficient parallel algorithm for transient simulation of power grids in VLSI systems Novel parallel Gauss-Seidel algorithm has been developed employing waveform relaxation iterations for application to power grid networks Proof of convergence of the proposed WR algorithm for power grid analysis is presented Unlike direct solvers, the new method is highly parallelizable and yields significant speed-ups Numerical examples are presented to demonstrate the validity and efficiency of the proposed method

Semiconductor package with improved power integrity

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip.

Decomposition of Coplanar and Multilayer Interconnect Structures with Split Power Distribution Planes for Hybrid Circuit-Field Analysis

Abstract: A novel technique for decomposing complex interconnect systems into signal propagation and power distribution parts is presented. The decomposition is performed around the discontinuities in the signal or return current paths. The decomposed structure is ideally suited for hybrid analysis where one part of the problem is modeled using circuit methods and the second part is analyzed using field solvers. The method significantly extends the available decomposition techniques in its generality and its applicability to a wide range of structures, including coplanar structures as well as structures containing conductive planes with voids such as splits, slits, or gaps. The decomposed structure offers the possibility of more efficient analysis compared to the analysis of the non-decomposed structure. Author(s) Biography Neven Orhanovic Neven Orhanovic received his B.S. degree in Electrical Engineering from the University of Zagreb, Croatia and his M.S. and Ph. D. degrees in Electrical and Computer Engineering from Oregon State University, Corvallis. From 1992 until 1999, he was with Interconnectix and Mentor Graphics Corp. developing numerical methods and simulation software in the area of interconnect analysis and interconnect synthesis. He is currently with Applied Simulation Technology working mainly on fullwave analysis methods. Dileep Divekar Dileep Divekar obtained a B.S. in Electrical Engineering from Pune University, Pune, India and M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, CA. He has worked in the areas of circuit simulation, semiconductor device modeling, static timing analysis and signal integrity. He is currently with Applied Simulation Technology. Norio Matsui Norio Matsui holds a Ph. D. from Waseda University, Tokyo and was a researcher in NTT Labs for over 16 years. During this period he developed noise simulation tools for Signal and Power Integrity as well as physical designs for high speed tele-switching systems. Apart from authoring numerous papers, he also lectured at Chiba University. He is currently President of Applied Simulation Technology and is actively involved in Power Integrity, Signal Integrity, and EMI/EMC solutions. Introduction The interconnect structures found in today’s printed circuit boards (PCBs) support several fundamental types of wave propagation. These fundamental modes of propagation can be separated into two categories: 1) modes that require two or more conductors to support the propagating waves; 2) modes of propagation that can be supported by single conductor containing a cavity or a void. The conductors that support the propagation can further have different shapes with widely varying dimensions and aspect ratios. Some of the conductors or voids in the conductors are thin and narrow and support mainly one dimensional (1D) propagation along the tangential (or longitudinal) direction. These 1D conductors or voids can usually be modeled accurately and efficiently using multiconductor transmission line models and conventional lumped element discontinuity models (Figure 1). Other conductors or voids are wide or thick and they can support more complex propagation in two or three dimensions (2D/3D). In most digital systems, the conductors used for signal propagation are mainly 1D while the conductors used for power distribution are 2D/3D. The 2D/3D conductors require more complex analysis techniques, which involve direct or indirect solutions of partial differential equations or integral equations in two or three space dimensions. Figure 1: Simple structure supporting mainly 1D propagation on the left and mainly 2D propagation on the right. For this example, the decomposition into 1D and 2D partitions is trivial (b). Although the same techniques used for the analysis of 2D/3D systems of conductors can be applied to 1D conductors, the procedure is inefficient in general. The main reason for the inefficiency of 2D/3D analysis methods when applied to 1D problems is in the presence of both very large and very small features in the structure. The ratio of the sizes of the smallest and larges features in the structure is directly related to the efficiency of 2D/3D analysis methods. A particular class of analysis approaches usually works best for a particular type of structures. It is therefore highly advantageous to decompose Circuit Model for Microstrip Meander Line on the Left (1D) 2D Field or Circuit Model for Microstrip Patch Interface Port 1D Propagation 2D Propagation

Modeling and impedance analysis of power distribution network in 3D ICs with TSVs

Abstract: This paper focuses on the modeling and analysis of different power distribution network (PDN) structures in 3D TSV ICs, including 3D full wave model and equivalent circuit model. In addition, a simplified equivalent circuit model of stacked PDN is proposed to analysis aspects influencing stacked PDN impedance, such as number of ground TSVs, number of TSV pairs and number of stacked layers. Analyses about how these aspects influencing total capacitance, inductance of stacked PDN and causing resonance in PDN self-impedance (Z11) are made in detail. What's more, power noise in different stacked PDN structures is calculated and analyzed in time domain to evaluate their power integrity features. Analysis in this paper can offer instructions for the design and analysis of on-chip PDN.

Decoupling Network Optimization by Swarm Intelligence

Abstract: In this chapter, the problem of decoupling network optimization is discussed in detail. Swarm intelligence is used for maintaining power integrity in high-speed systems. The optimum number of capacitors and their values are selected to meet the target impedance of the system.