Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integration

Abstract: An analysis of through silicon via (TSV) effects on next-generation super-high-speed transmission and power integrity package design for 2.5D modules with a highperformance central processing unit (CPU) or other 300A-class LSI mounted and 3D LSI is described in this paper.

Deriving voltage tolerance specification for processor circuit design

Abstract: A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous switching noise (SSN), and voltage regulation module (VRM) tolerance This method has been serving well for power tolerance specifications of multiple generations of IBM processor designs However, the methodology needs further refinement to design the off-chip serial interfaces As the interfaces are increasing in frequency, the voltage levels and swings are minimized to meet the performance criteria of maximizing the data transfer rate per watt

The high speed low noise multi-data processing signal process circuit research of remote sensing

Abstract: The high speed, low noise and integration characteristic are the main technology and the main development directions on the signal process circuit of the image sensor, especially in high resolution remote sensing. With these developments, the high noise limiting circuits, high speed data transfer system and the integrated design of the signal process circuit become more and more important. Therefore the requirement of the circuit system simulation is more and more important during the system design and PCB board design process. A CCD signal process circuit system which has the high speed, low noise and several selectable operate modes function was designed and certificated in this paper, during the CCD signal process circuit system design, simulation was made which include the signal integrity and the power integrity. The important devices such as FPGA and the DDR2 device were simulated, using the power integrity simulation the sensitive power planes of the FPGA on the PCB was modified to make the circuit operate more stabilize on a higher frequency. The main clock path and the high speed data path of the PCB board were simulated with the signal integrity. All the simulation works make the signal process circuit system’s image’s SNR value get higher and make the circuit system could operate well on higher frequency. In the board testing process, the PCB time diagrams were listed on the testing chapter and the wave’s parameter meets the request. The real time diagram and the simulated result of the PCB board was listed respectively. The CCD signal process circuit system’s images’ SNR (Signal Noise Ratio) value, the 14bit AFE slew rate and the data transfer frequency is listed in the paper respective.

Radio Frequency Interference Due to Power Plane Radiation and Mitigation Using RFI and PI Co-Optimized Design in Mobile Platforms

Abstract: This paper’s main focus is to study the noise radiation risk from motherboard power planes, including the mechanism of power plane radiation. A design for a power plane that is optimized for radio frequency interference (RFI) and power integrity (PI) is studied and simulation and measurement results are presented. This design has been proposed to reduce the level of RFI radiated from the power plane to the nearby antennas.

Body-Bias Voltage Generation

Abstract: In this chapter we will discuss about the choice of generating body-bias voltage generation inside or outside of the SoCs. For both cases advantages and disadvantages will be highlighted. The second step of this part treats of the load seen by a Body-Bias GENerator (BBGEN), embedded or not. These exercises will be helpful to determine the list of main specifications that should have a BBGEN. Each specification elements will be detailed. As for any analogue circuit, knowledge of the output load is definitely essential to realize a successful design. After that we will elaborate on some way to build and design a BBGEN and how to implement it at SoC level.