Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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01 Jan 2004
TL;DR: Which input parameter need to be accurate in order to obtain accurate simulation results is shown in a sensitivity analysis for high-frequency on-chip power noise distribution.
Abstract: Power integrity gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip AInoise. Some simulation methodologies, e.g. RAPiD, are known for simulation. Collecting and processing the required input for these simulations is very time consuming. This paper presents a sensitivity analysis for high-frequency on-chip power noise distribution, The results help to optimize the effort required to achieve the needed accuracy of simulation. A generic description of the on-chip AI-noise simulation methodology is shown. In particular the required input data is described. A sensitivity analysis has been performed to quantify the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5~ to 2.0~ compared to a nominal case. The maximum AI-noise is plotted depending on the input parameter. The comparison to the nominal case shows which of the parameters have a high, medium or low impact on the simulated AI-noise. This paper shows which input parameter need to he accurate in order to obtain accurate simulation results.
25 Sep 2019
TL;DR: By applying the analysis results to the design stage, the electromagnetic wave performance is improved, and several ways to secure SI and PI using various methods are introduced to reduce the PCB design cost, and improve the reliability of the electromagnetic waves.
Abstract: Currently, automaker companies are applying mechanical / electronic technologies to various automotive parts for decreasing vehicle vibration. One of the best ways to reduce engine vibration is to apply an active engine control mount(ACM). This paper's main issue is to decrease design errors by signal malfunction and electromagnetic compatibility(EMC) [1][2] in the design phase of ACM electronic control module development. To do this process, we analyzed the power integrity(PI) analysis which is one of Computer Aided Engineering(CAE) methods. Also, we introduce several ways to secure SI and PI using various methods. So, by applying the analysis results to the design stage, we improved the electromagnetic wave performance. Also, we can reduce the PCB design cost, and improved the reliability of the electromagnetic wave.
01 Jan 2017
TL;DR: In this article, the authors describe the steps used to design an alternative metasurface which is based on Circular Complementary Split Ring (CCSR) formation at 5.8 GHz.
Abstract: This research paper describes the steps used to design an alternative metasurface which is based on Circular Complementary Split Ring (CCSR) formation at 5.8 GHz. All the 3D modelling was conducted using specialized EM simulation software that utilizes Eigen algorithm to solve different frequency modes that can resonate within the CCSR structure itself. The final design will be then fabricated using a precise laser CNC machine to achieve a better dimension as closely as possible to the simulation dimension. By using laser CNC, this step will able to overcome generic PCB design issue related to via’s placement, signal integrity, power integrity and multilayer designs. Completed CCSR metasurface will be able to mitigate or block unwanted EM mode from flowing to its neighbouring sensitive area which can affect the entire component performance due to unseen harmonics.
14 Mar 2021
TL;DR: In this paper, the impact of supply noise on various designs for nano-meter VLSI and discuss the potential opportunities that may provide PI designers with additional design flexibility, which may enable them to add additional die area to reduce the unwanted supply noise.
Abstract: With VLSI keeps scaling down, power supply noise margin gets further diminished due to the relatively stable threshold voltage. On the other hand, the continuously growing current density incurs additional supply noise, which easily violates the pre-set power integrity noise margin threshold. Thus, power integrity (PI) designers have to either conduct repeated back-tracking or add additional die area to reduce the unwanted supply noise, which is both cost and time consuming. A very natural question that may arise is then what happens if this noise margin threshold is violated? In this paper, we will investigate the impact of supply noise on various designs for nano-meter VLSI and discuss the potential opportunities that may provide PI designers with additional design flexibility.
TL;DR: In this paper, the authors proposed the modeling of the power/ground plane which includes complex dielectric permittivity and loss tangent for the power and ground coupled noise.
Abstract: In this paper, we propose the modeling of the power/ground plane which includes complex dielectric permittivity and loss tangent for the power/ground coupled noise. In order to estimate the effects of the dielectric substrate for the coupled noise, we used full-wave simulators, HFSS(High Frequency Structure Simulation) and MWS(MicroWave Studio). The simulated results for the commercial substrates are compared with the measured values. TLM(Transmission Line Method) was used for the calculation of power plane impedance using Debye model which depicts the dielectric loss of PCB. Finally, impedance from proposed circuit model showed very good coincidence to the measured data.