scispace - formally typeset
Search or ask a question
Topic

Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


Papers
More filters
Proceedings ArticleDOI
01 Jan 2016
TL;DR: A practical power supply design method for the display panel of smartphone to reduce the voltage stress over the internal MOSFET of the power supply for more reliable operation.
Abstract: This paper introduces a practical power supply design method for the display panel of smartphone. The specific goal of this design method is to reduce the voltage stress over the internal MOSFET of the power supply for more reliable operation. A power integrity analysis is conducted to evaluate a factor which increases the voltage stress over the internal MOSFET. Based on this analysis, two PCB layouts are designed for case studies. Reduced voltage stress is verified in the case study.
Journal ArticleDOI
TL;DR: The 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI) as discussed by the authors was the third year of collaboration between the IEEE EMC Society and the IBIS Open Forum.
Abstract: The 2022 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI) featured the third year of collaboration between the IEEE EMC Society and the IBIS Open Forum. Two events adding SI and PI content to the symposium included the IBIS “Ask the Experts” panel on August 4th and the IBIS Open Forum Summit on August 5th.
Proceedings ArticleDOI
01 Dec 2011
TL;DR: A mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs is proposed in order to ensure the power integrity of the logic load during switching.
Abstract: The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.
01 Dec 2010
TL;DR: A high-pin-count and thin embedded-LSI package to realize nextgeneration's mobile terminals and the five-stage process for reducing the number of metal layers is described by means of the electrical simulation.
Abstract: We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize nextgeneration's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using thecoreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of thethree points, the five-stage process for reducing the number of metal layers is described by means of the electricalsimulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points playimportant roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the numberof metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we shouldconfirm the SI characteristics.
Journal ArticleDOI
TL;DR: A decoupling-capacitors (Decaps) placement technique to reduce power distribution network impedance (Zpdn) and a circuit design procedure regarding power supply fluctuation and a bit error rate lower than 1 × 10−12 on backplane transmission.
Abstract: A transceiver for a 25.8Gbps/lane with a re-timer IC has been developed for information and communication equipment. Since a 1-unit interval (UI) is very narrow at 38.8 ps at 25.8Gbps, power integrity (PI) jitter due to power supply fluctuation cannot be ignored. In this paper, we proposed a decoupling-capacitors (Decaps) placement technique to reduce power distribution network impedance (Zpdn) and a circuit design procedure regarding power supply fluctuation. The re-timer IC adopted from the proposed procedure achieved a bit error rate (BER) lower than 1 × 10−12 on backplane transmission with an insertion loss (IL) of 40 dB.

Network Information
Related Topics (5)
Integrated circuit
82.7K papers, 1M citations
80% related
Antenna measurement
39.6K papers, 494.4K citations
78% related
Antenna (radio)
208K papers, 1.8M citations
77% related
CMOS
81.3K papers, 1.1M citations
77% related
Dipole antenna
38K papers, 513.8K citations
77% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852