Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Microprocessor power noise measurements with different levels of resource occupancy

Abstract: Power noise waveforms of a 32-bit microprocessor were on-chip measured in a 90-nm CMOS technology. A dedicated measurement system combines an embedded programming environment and a measurement flow that ensures acquisition of noise waveforms during designated arithmetic operation. Power noise exhibits clear relation with the contents of computation, where the magnitude of power noise reflects the occupancy ratio of computing resources of a microprocessor. The level of correlation is shown to be different among static and dynamic portions of power noise. It is concluded that practical power noise analysis requires the higher-level abstraction of a large-scale integrated digital system.

A Study on an IBIS-like Model to Ensure Signal/Power Integrity for I/O Drivers

Abstract: This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last decade for I/O drivers. The study includes the IBIS-like modeling techniques including package parasitics. The IBIS-like model has been analyzed mathematically and validated using 28 nm CMOS technology of TSMC foundry. For validation purposes, the predriver circuit and the I/O buffers have been simulated with 0.9 V of VDD. The IBIS-like nonlinear models have been created using Simulink® and the results have been compared with the Electronic Design Automation (EDA) tools. The Simulink® results show a Normalized Mean Square Error (NMSE) of - 51.91 dB with 1.63 sec of CPU time for the case of pull-up current, -49.42 dB with 474.34 msec of CPU time for the case of pulldown current response. In the case of output voltage response, the NMSE is - 48.33 dB and 2.12 sec of CPU time.

Scaling system performance through packaging and interconnect: A study in networking applications

Abstract: High end networking and computing applications continue to drive silicon technologies to higher data rates, increased storage capacity, and increased bandwidth. Interfaces are transitioning more toward serial technologies, even for short distance data transfer. Voltage supply rails continue to drop and consequently, the noise margins become reduced, even with increasing numbers of simultaneously switched signals. The ratio of leakage current to active current is also increasing for high performance silicon processes, as is the demand for more instantaneous switching current. Power integrity and power distribution design becomes a more prevalent issue in electrical design as it dictates the efficiency of current draw available to switch on-chip circuits. Silicon integration and device scaling still leads to overall higher performance, but there are practical limits to the yield and assembly reliability of very large die. Packaging begins to play a more critical role in the improvement of performance through scaling of interconnect. This paper will examine the design tradeoffs for high end networking chips for performance and cost optimization. Two examples are shown where packaging design is directly linked to enabling system level performance impact.

Mesh-based impedance sensitivity formulation for DC/AC Power Integrity design and diagnosis

Abstract: Accurate Power Distribution Network (PDN) design is crucial for Signal/Power Integrity (SI/PI) and Electromagnetic Interference (EMI) compliance. Achieving target power-ground (PG) noise levels for low power complex PDNs requires several design and analysis cycles. Although several classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools are limited e.g. parametric design space exploration using multiple forward analysis. In this work, a frequency domain mesh-based sensitivity formulation for DC and AC impedance of PDNs is proposed. The two main objectives include: (i) highlighting layout regions to the designer for maximum impact in achieving target specifications and (ii) predicting the results of a design variant with mesh-based sensitivity information from the base-design. The time required for updating the results for the design variant is negligible compared to a complete re-simulation.

Method of signal integrity and power integrity analysis for address bus

Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.