Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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11 May 2022
TL;DR: In this article , a virtual prototyping technique is proposed to design 3D power supply on chip (3D power SoC), which integrates Si based IC, Gallium Nitride (GaN) power devices and passive devices realizes high efficiency at high frequency switching and high power density.
Abstract: 3D power supply on chip (3D power SoC), which integrates Si based IC, Gallium Nitride (GaN) power devices and passive devices realizes high efficiency at high frequency switching and high-power density. Miniaturization makes 3D power SoC high temperature, thus, we have to take into consideration of the temperature effect when we design 3D power SoC. In this paper, we propose a virtual prototyping technique, which is coupling of thermal-device, heat conduction, thermal-electromagnetic, and thermal-circuit simulation to design the 3D power supply on chip.
01 May 2022
TL;DR: In this article , the power integrity performance of different floorplans, PKG PDN designs, and current scenarios of the multiple blocks was studied. But, the performance of the floorplan was not analyzed.
Abstract: High cost of high-end silicon manufacturing processes are squeezing die sizes and pushing multiple blocks in a single power domain to be placed in narrow and long area. Consequently, these blocks have poor power integrity environment due to narrow and long shape PKG PDNs following their narrow and long shaped die floorplan. The several power integrity performances are studied according to floorplans, PKG PDN designs, and current scenarios of the multiple blocks. The narrower and longer shaped floorplan leads higher PKG PDN impedance due to lower sharing ability of on-die decoupling capacitors, and resulting larger power domain voltage drop. These voltage drops become larger as di/dt level of each scenario is bigger and frequently happens.
10 Nov 2009
TL;DR: How multidimensional parametrization, optimization, and synthesis need to be taken into account while creating simulator flows that will enable early design of digital microelectronics packages and RF frontend integrated circuits is discussed.
Abstract: High-speed applications in radio frequency, mixed-signal, and digital packaged electronics now necessitate the use of 3D, full-wave electromagnetic field solvers. The widely varied applications now involved in System-in-Package (SiP), System-on-Chip (SoC), Package-on-Package (PoP), three-dimensional integrated circuit (3DIC) technology including through-Silicon vias (TSVs) range from design and verification of the power delivery network (PDN), signal integrity and channel modeling of high-speed serial and parallel links, electromagnetic interference (EMI) and radiation, simultaneous switching noise (SSN), and voltage drop and ground bounce modeling amongst others. In addition, designers need to co-design chip I/O, packages, and board subsections nearly simultaneously in order to satisfy system-level signal integrity (SI), power integrity (PI), and EMI constraints. EM field solution is needed not merely in the complete verification of such systems but also in early design. Unfortunately, most EM simulators continue to be verification tools, merely masquerading as design tools. In this paper we discuss the challenges and needs associated with EM-aware design. In particular, we focus on digital microelectronics packages and RF frontend integrated circuits. We discuss how multidimensional parametrization, optimization, and synthesis need to be taken into account while creating simulator flows that will enable early design.
NEC1
TL;DR: In this paper, a fast power integrity analysis system to realize the chip-package-board co-design is described, which contributes to the increase of design efficiency in early product development stage followed by reducing the time loss due to the rework in the development process.
Abstract: Fast power integrity analysis system to realize the chip-package-board co-design is described As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more These difficulties often bring re-designs of board and package layouts Short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required for reducing the time loss by the rework and increase design efficiency, This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process
01 Jan 2010
TL;DR: There are a number of software tools and techniques to provide fast analysis of a single power/ground pair of planes, but they are based on two dimensional analysis, making the solution time unacceptably long for real world PCB sizes with complex plane shapes.
Abstract: Introduction Rapid power distribution network (PDN) analysis for complex printed circuit board (PCB) stack ups is very important to insure proper functioning of the PDN. While there are a number of software tools and techniques to provide fast analysis of a single power/ground pair of planes, they are based on two dimensional analysis. Adding the third dimension usually requires a fullwave approach, making the solution time unacceptably long for real world PCB sizes with complex plane shapes.