Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

A Versatile Platform towards High Reliability Compact Package for Digital Chips

Abstract: A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye diagram opening for 10 Gbps rate signal, and power integrity. The mechanical targets are thermal warpage management and easy handling and assembly of the interposer in order to build a reliable module. This demonstrator integrates three large top dies on a packaging platform constituted of a 700 mm2 mid-density passive silicon interposer, reported on a 45 × 45 mm2 ceramic substrate. The interposer design rests on four copper layers: the three last copper layers of B55 (C65-based) technology for the front side, and a thick 4 to 8 µm copper redistribution layer technology for the backside. The through-silicon-via technology used is a via-last technology. At 5 GHz, this design achieves 0.22 dB/mm propagation loss on the front side, and 0.1 dB loss per TSV with high resistivity silicon substrate. Besides, the silicon interposer is deemed suitable for a 19 W processor die power supply, exhibiting 11 mV drop voltage between a backside bump and two front side bumps. After design and electrical studies, the manufacturing is presented from the interposer process steps to the assembly steps and characterized thanks to RF and DC test patterns. TSV's and the three types of bumps resistances are given. Focus is made on important topics for higher performances such as inter-die distance reduction or front side layers typology, and on important topics for high reliability such as the silicon interposer's warpage behavior or the under-filling process development under large dies.

Deep dive into DDR3 interface jitter contributors

Abstract: This paper presents a case study of DDR3 interface timing jitter of a DDR subsystem on an evaluation module. The total jitter was separated into various Signal Integrity (SI) and Power Integrity (PI) effects, including signal crosstalk, impedance discontinuities, simultaneous switching noise (SSN), and inter-symbol interference (ISI). Good correlation was achieved between the simulation environment and silicon measurements. The paper also discusses how the study helped guide the package selection for a family of SoC designs.

Electrical modeling and design

Abstract: Electrical analysis is extremely important for advanced packaging as it should provide chips with signal and power distributions. In this chapter, we focus on the electrical modeling and characterization of TSV packages. First, the basic knowledge of signal and power integrity is briefly depicted. Second, the modeling, characterization, and design of TSV packages are presented in detail. The circuit models are developed for TSV pair and TSV array, and the effects of metal-oxide-semiconductor capacitance and floating silicon substrate are considered and treated appropriately. Third, the TSV-based 3-D power distribution network is characterized based on the equivalent circuit model. At last, dummy TSVs are utilized for the design of integrated passive devices, which are believed to be beneficial for saving valuable chip areas.

Advanced Measurement and Simulation Approach for DDR5 On-chip SI/PI with the Probing Package

Abstract: As the operation of server system is accelerated, the importance of signal integrity (SI) and power integrity (PI) measurement methodology and modeling of dual in line memory module (DIMM) products is increasing. In this paper, we introduce the advanced methodology for on-chip SI/PI measurement and DRAM signal recovery with the DDR5 probing package development. Comparing with the conventional interposer, a new method of probing package has proved to be advantageous for high-speed signal measurement and signal recovery, and it can also be used as a useful tool for DRAM on-chip SI measurement and signal prediction in post DDR5 speed (beyond 6.4 Gbps).