Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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Patent•
27 Dec 2018TL;DR: In this article, the authors proposed a power delivery network analysis of the memory unit I/O power domain, which includes signal and power integrity analysis for a memory unit IC power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the IC, and determining whether the characteristics of the current waveforms and the expected waveforms are within a tolerance limit.
Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.
17 May 2016
TL;DR: By using this SA method, the P/G pins assignment of a large-scale BGA package with blocks of core, inputs/outputs and differential pairs can be generated in a few minutes automatically.
Abstract: In this paper, a package P/G pins assignment optimization method based on simulated annealing (SA) is proposed. Two objective functions describing power integrity (PI) and signal integrity (SI) are introduced. The basic flow of SA is presented, with the redefinition of the neighborhood of solution in SA, which ensures the feasibility in iteration. A 49×49 pinout example generated by the proposed SA method is presented, the compression of the SA example and the product from Xilinx is provided. By using this SA method, the P/G pins assignment of a large-scale BGA package with blocks of core, inputs/outputs and differential pairs can be generated in a few minutes automatically.
Patent•
24 Mar 2020TL;DR: In this article, a power integrity analysis of an integrated circuit is performed to estimate power induced noise in a double-glitch capture mode, and data is then provided that characterizes the performed double glitch capture mode power integrity of the integrated circuit.
Abstract: Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.
01 Dec 2016
TL;DR: In this article, the authors present three printed circuit board designs with different power distribution topologies and show through measurement that a previously proposed PDN design based on Power Transmission Line (PTL) concept is less susceptible to coupling from signal lines.
Abstract: Transmission lines carrying high speed I/O signals can couple significant amount of electromagnetic energy to power distribution network (PDN) which can then adversely affect signal and power integrity of the entire electrical system. Similarly the reverse is also true. In this paper we present three printed circuit board designs with different power distribution topologies and show through measurement that a previously proposed PDN design based on Power Transmission Line (PTL) concept is less susceptible to coupling from signal lines.
01 Jan 2015
TL;DR: In this paper, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs.
Abstract: As traditional CMOS scaling pace gradually slows down, three-dimensional (3D) integration offers another dimension of in the ”More-than-Moore” era. In this dissertation, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs. Partial Element Equivalent Circuit (PEEC) method with layered Green’s function is studied here, since it consumes less computational resources and provides better physical insight to model the interconnects in 3DIC for high-speed digital circuits. The work is organized as a series of papers. The first paper reviewed the fundamental methods to derive layered Green’s function in spectral domain using discrete complex image method (DCIM) and analyzed the effects of each Green function terms to model silicon interconnects. The second paper proposed a unique method to extract poles near branch cut in complex kp plane, to accurately extract surface wave effects. The last paper proposed a new equivalent circuit model for coplanar waveguide (CPW) structure on 3DIC. The silicon effects on series inductance were also studied by employing the modified Green functions with semiconductor images at a complex distance from spectral-domain analysis.