Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Neuro-Fuzzy Nonlinear Dynamic Modelling for Signal Integrity Simulation

Abstract: This chapter presents a multiport empirical model for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about I/O interface are recorded from large signal simulation setup. The model’s functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port. Moreover, a comparative analysis between the artificial neural networks (ANNs) and adaptive neuro-fuzzy inference (ANFIS) models by exploring their modelling capabilities regarding the mathematical structures and identification algorithms in providing an accurate and computational effective behavioral model for the I/O buffers nonlinear dynamic behavior is investigated. The proposed model of the two-port I/O buffer is extracted from observable large-signal I/O current and voltages transient data. The training and computational performances along with the prediction accuracy of both modelling approaches are evaluated. The ANFIS model has better prediction accuracy by improving the normalized mean squared error (NMSE) by −13.5 dB while reducing by 11.66% the parameters’ number in cross-validation signal integrity scenario.

Electrical design and analysis from die level to system level in advanced semiconductor engineering group

Abstract: The scope of advanced semiconductor engineering (ASE) Inc. developments on microwave field including integration passive device (IPD), system-in-package (SiP), through silicon via (TSV), signal integrity(SI) and power integrity (PI) on system level, and Co-design/Co-simulation together with device modeling, integrated system analysis, measurement techniques over 60GHz, and design automatic platform have been presented. In this paper, the major development techniques at ASE will be introduced.

S-Parameters for High Speed Digital Engineers: A Beginner's Guide

Abstract: Scattering or S-parameters, have been used in RF applications for more than 70 years [1]. However, it has only been in the last 30 years they have been used extensively in high-speed digital applications, such as signal integrity, power integrity and EMC, and then only slowly accepted by the general community.

Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk

Abstract: Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.