Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

A novel hierarchical radial tree based on constructal theory for PCB power plane

Abstract: This paper proposes a hierarchical radial tree distribution network based on constructal theory for optimal direct current performance in printed circuit board power plane. The optimal radial tree dimensions of each order are obtained for optimal voltage drop and resistance. The constraints are the total areas of the plane and the high conductivity paths. The degrees of freedom are the width/length ratio H i /L i of the constructal block, high conductivity paths ratio D i+1 /D i (i=1, 2, etc). According to constructal theory, the optimal performance consists of constructing the giving area in a sequence of building blocks from the smallest size toward larger sizes hierarchically. High assembly level is not necessary. The optimal order is 12 for the designed tree. Then a radial PCB power plane is developed based on the radial tree which illustrates that the designed plane has multifunctions of low voltage drop, current robustness, equidistribution, compactness and effective noise isolation while maintaining a relatively simple design of geometry.

Power & Ground Bridging Trace Design for Improved Power Integrity

Abstract: Nowadays, demand for slimmer and better performance consumer electronics increases dramatically. As PCB size keeps shrinking, power integrity issues such as high voltage drop and power loss arise due to lack of power and ground planes and broken power and ground shapes caused by densely-populated signal vias. In this paper, a novel design of power and ground bridging trace, placed between anti-pads of through-hole vias, the voltage drop issue can be greatly improved.

Modeling and Optimization for High-speed Links and 3D IC

Abstract: The advance of modern integrated circuit (IC) processes has supported increasing date rates on chip-to-chip communications in many consumer and professional applications, such as multimedia and optical networking. Serial links have successfully evolved and achieved the bit-rate of several tens of Gb/s per channel by applying new generations of IC process and advanced circuit techniques. However, as process technologies further scale down, severe process variations significantly impact the performance of high speed serial links and makes today's circuit designs have to be optimized not only for nominal performance but also for a reasonable yield. On the other hand, three-dimensional (3D) IC provides a smaller form factor, higher performance, and lower power consumption than conventional 2D integration by stacking multiple dies vertically. Through-silicon-via (TSV) enables the vertical connectivity between stacked dies or interposer and is a key technology for 3D IC. However, electrical signaling over TSVs presents a unique set of design challenges and thus requires accurate modeling and detailed signal and power integrity analysis.In this research, the bottlenecks in TSV modeling, variation-aware circuit optimization and efficient performance evaluation for high bit-rate applications are analyzed, and solutions are presented. A simple yet accurate pair-based model for multi-port TSV networks (e.g., coupled TSV array) is proposed by decomposing the network into a number of TSV pairs and then applying circuit models for each TSV pair. This methodology is first verified against full-wave electromagnetic (EM) simulation for up to 20GHz and subsequently employed for a variety of examples of signal and power integrity analysis. For high speed serial links, an optimization framework is proposed for the joint design time and post-silicon tuning optimization for digitally tuned analog circuits, and can be used to maximize the yield in serial link transmitter design and the phase-locked-loop (PLL) design subject to the area and power constraints. Moreover, an efficient mathematical method is proposed to capture the worst-case data-dependent jitter and noise without lengthy simulations. These modeling and optimization methodologies can be applied to accurately explore the chip-to-chip integration and signaling schemes at early design stage in today's and tomorrow's 3D IC and high speed serial link design.

Integral Equation Technique for the Simulation of Signal Integrity and Power Integrity

Abstract: Signal integrity and power integrity are the crit- ical issues for high-speed digital circuits. This paper re- views the state-of-the-arts of the integral equation technique used for the simulation of signal integrity and power in- tegrity including the power and ground planes. Accord- ing to the different circuit boundary conditions, the ap- plied integral equation methods can be classified into mode method/segment method, image method, and equivalent electromagnetic currents method. The mode/segment and image method is used for power and ground planes with rectangular shapes, while the equivalent electromagnetic currents method is efficient for power and ground planes with arbitrary shapes. The most important part of these in- tegral equations is the integral kernels (Green's functions). The integral kernels are derived for different circuit bound- aries. Both the theoretical formula and simulation results are present, which are then verified with other available sim- ulation methods and measurement results.

Analysis of novel technology for power and signal integrity using a metal particle conductive layer

Abstract: Power integrity (PI) has been an important technological issue in the field of electronic circuits and systems. It has been addressed in important papers using several different approaches [1][2]. The latest concept of the best PI condition is a low impedance between the power and ground lines or planes, that can be maintained regardless of the clock frequency, even in the GHz region. A novel technology was used in our previous study, in which a metal particle conductive layer (MPCL) was used instead of a copper plane [3][4]. This structure improved the PI for any clock frequency, particularly in the GHz region. The MPCLs consist of micrometer sized silver flakes (SF) and binder resin. In this study, we used an epoxy as a binder for conductive paste, polyimide (PI) copper clad laminate (CCL) and 60 µm thickness prepreg as the inner dielectric of test coupons. These are general-use material so that they can be made easily, and apply to printed circuit boards (PCBs) and package substrates (PKGs). It has been found from transmission line test coupon measurements, that energy propagation time and frequency characteristics, are strongly affected by the metal particle content and chemical composition. From power/GND plane test coupon measurements, MPCL can reduce Z11 about 70% compared with copper plane from 1 to 5GHz frequency region. In this paper, we will show the detailed phenomena of MPCL, exceeding the region of usual transmission line theory, and MPCL adaptability to commercial materials of PCB and PKG.