Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Integrated Circuit Characterisation Using Low-Cost Coaxial Probe Measurement

Abstract: This paper presents a method to characterise integrated circuit (IC) using a low cost coaxial probe. The characteristic impedance of the IC can be used in both time and frequency domain, where it significantly improves the behavioral model of a printed circuit board (PCB) circuitry which is currently being used with limited functionality. S-parameter results obtained from the measurement using the coaxial probe was combined in the simulation model of the PCB which was simulated using three-dimensional (3D) full wave simulation. A comparison between the measurement and simulation results was made and it shows that the measured IC characteristic impedance through the devised low cost probe method produces good correlation up to 1,000 MHz. This study concludes that the feasibility of using the proposed technique for impedance characterisation of IC to be included into the PCB circuitry would provide a better understanding of signal and power integrity, and electromagnetic compatibility (EMC).

Simultaneous Switching Noise Analysis for High-Speed Interface

Abstract: This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

New PC board structure for power supply technology over GHz frequency verificated with 32bit SSN driver system

Abstract: Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.

Analytical Models for Embedded Discrete and Thin Film Capacitors in Multilayered Printed Circuits

Abstract: Analytical models are proposed for accurate characterization of embedded capacitors in multilayered printed circuit stackups. In the proposed algorithm, a printed circuit board (PCB) is represented as a stack of resonant cavities with embedded thin film and discrete capacitors modeled as layers and components, respectively, in an inner cavity. This representation allows for a mathematical model in the form of finite continued fractions. The frequency domain response of the proposed model is observed in good agreement with data from numerical electromagnetic (EM) simulations, which validate its accuracy. The developed model is intended for quick and practical power integrity (PI) analysis of printed circuits with idefinite number of stackup layers.

Impedance Modeling and Analysis of Multi-stacked On-chip Power Distribution Network in 3D ICs

Abstract: Abstract An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in threedimensional integrated circuits (3D ICs). This paper proposed a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multistacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix . In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.