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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


Papers
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Journal ArticleDOI
TL;DR: The method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation is analyzed and verified.
Abstract: Recently, mobile devices have evolved into small computers with various functions according to user requirements. Careful attention must be paid to the design of the power supply network for the stable operation of the application processor (AP), the wireless communication modem, the high performance camera, and the various interfaces of the mobile device to implement various functions of the mobile device. In this paper, we analyzed and verified the method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation. The proposed wired power supply network design method can be applied to various applications including high-speed signal transmission line in addition to mobile applications.
Proceedings ArticleDOI
24 Sep 2015
TL;DR: In this article, the effectiveness of MIM capacitance and MOS capacitance is compared and the authors focus on PDN analysis to describe the change in behavior and the validation results to show the gap when MIM is completely removed.
Abstract: Capacitance is very important in High Speed I/O power integrity network design There are different form of capacitors being used on the High Speed I/O Power Integrity Network to ensure the performance of the circuit In this paper, the effectiveness of MIM capacitance and MOS capacitance is compared MIM capacitance comes in bulk quantity but placed further away from the HSIO circuits While MOS capacitance comes in considerably lower quantity but placed closer to the HSIO circuits As such, there is a performance trade-off during the power integrity design considering the two different capacitances While MOS capacitance is the preferred choice, the introduction of MIM capacitance has become an attractive option; as it offers much more capacitance at lower price Can MOS capacitance be replaced by the MIM capacitance? The discussion will focus on PDN analysis to describe the change in behavior and the validation results to show the gap when MIM capacitance is completely removed
Proceedings ArticleDOI
01 Dec 2012
TL;DR: A VCO detector circuit with broadband and sensitivity characterizations is designed and used to evaluate on-package DC IR-drop and signal-integrity and these effects can be observed from the relationship between voltage, frequency, and the trend of the output sweeps.
Abstract: Nowadays, ICs work in high speed and high frequency environments, the effects that package brings has become more and more obvious. These effects can be classified as signal integrity (SI) and power integrity (PI). In this paper, A VCO detector circuit with broadband and sensitivity characterizations is designed and used to evaluate on-package DC IR-drop and signal-integrity. The package structure we used in this paper is wire-BGA. The methods for testing IR-drop and SI effects by this wide tuning range and high tuning sensitivity VCO with different package circuit design were shown in this research. Thus, these effects can be observed from the relationship between voltage, frequency, and the trend of the output sweeps.
Dissertation
01 Jan 2010
TL;DR: In this paper, the worst-case voltage drop in a microprocessor run-trace is derived based on time-based power simulations, considering full-chip total power in several time-resolutions, frequency-based approaches using FFT and wavelets, and the spatial locality of switching activity.
Abstract: In order to decrease performance pessimism due to supply voltage uncertainties in integrated circuits, detailed power integrity analysis is necessary. Knowing the worstcase voltage drop that the circuit will encounter is a step towards this goal. The voltage drop is input-dependent, which means the outcome depends on how the chip is used. In this thesis, methods to extract the worst-case clock cycle out of a microprocessor run-trace are developed. The methods considered are based on time-based power simulations, considering full-chip total power in several time-resolutions, frequency based approaches using FFT and wavelets, and the spatial locality of switching activity. SPICE voltage drop simulations are performed while considering R and L components of the power grid, as well as decoupling capacitance and the gate switching extracted from the run-trace. Results show that the voltage drops found when focusing on spatial locality exceed the previous worst-case for the chip design by a factor of 2. This method considers the worst-case power grid node, finding the time-instance where maximum power dissipation of its adjacent nodes coincides with the maximum power dissipation of the chip’s CPU core. Attempts at alleviating these sparse and localized large voltage drops are performed through the use of skew-spreading. This method is shown to decrease the largest voltage drop found by over 20%.
Proceedings ArticleDOI
01 Oct 2010
TL;DR: In this article, a near-field approach is used to estimate the radiation of a package by using a simulation tool, and several factors were investigated in this study to conclude some useful concepts for package layout design.
Abstract: At the present time, the package design faces demands, including the high-speed switching, low-voltage bias and minimization. The high-speed signals may induce not only signal integrity and power integrity issues, but also cause radiation and electromagnetic interference (EMI) problems. To evaluate a package design, near-field scan is a useful technique to investigate the radiation behavior. Our study is based on this near-field approach to estimate the radiation of a package by using a simulation tool. Several factors were investigated in this study. From the near-field results, we could conclude some useful concepts for package layout design.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852