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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings ArticleDOI
04 Apr 2023
TL;DR: In this article , an innovative power integrity simulation methodology is proposed using open-source simulators as to simulate the power drop across the power delivery network (PDN) of a system-on-chip.
Abstract: An innovative power integrity simulation methodology is proposed in this work, using open-source simulators as to simulate the power drop across the power delivery network (PDN) of a system-on-chip. As an open-source simulator, the NgSPICE was used along with the PySPICE module, which enables accurate and large-scale integration power integrity analysis. The case study circuit vehicle, a D-latch 9-stages ring oscillator, was implemented in a 16 nm process and used as to validate the proposed Python framework. In the proposed methodology, the circuit vehicle netlist and the PDN were described in. csv file format as to be easily manipulated using Python programming. Three different power delivery network topologies were addressed and power grid parasitic-aware simulations were performed. Each power delivery network scenario was examined individually for several values of resistance, capacitance and inductance of the power grid network.
Proceedings ArticleDOI
10 Aug 2022
TL;DR: In this paper , the authors present a system packaging scheme, which encapsulates the key components of PFC and LLC step-down circuits, rectifier soft bridge, and two-stage stepdown circuit, which realizes the functions of 150V-250V DC wide voltage input, 20V and 5V DC output.
Abstract: With the development of portable electronic equipment, the power density and volume of power adapters have attracted more and more attention. Using high-frequency switching elements to reduce the volume of inductive elements, PFC circuit to improve the power factor and reduce the volume of capacitive elements, using highly integrated elements is a common method. When using high-frequency switching elements, the power integrity, signal integrity, and impedance matching of high-frequency signal lines should be considered. The design of power management SOC faces the disadvantages of the long development cycle and high investment cost.This paper presents a system packaging scheme, which encapsulates the key components of PFC and LLC step-down circuits, rectifier soft bridge, and two-stage step-down circuit [1]. The module realizes the functions of 150V-250V DC wide voltage input, 20V and 5V DC output. The package interconnection model is established and imported into ANSYS software for simulation. The power integrity of the power supply network is analyzed, the planar resonance point of the power supply is explored, and the decoupling optimization is carried out [2]. Through simulation analysis, the layout of power and signal wiring is optimized. Through optimization design, the module achieves the maximum voltage drop of 5V within 5%, and the PDN meets the impedance requirements within the target frequency, meeting the design requirements. The miniaturization and integration of modules can be realized by system-level packaging of DC-DC circuits. The results show that the scheme is advanced and feasible.
Journal ArticleDOI
01 Jan 2011
TL;DR: In this article, the authors describe the power integrity and signal integrity of Adv-SLC and the capability to reduce total layer count with considering X-talk, to reduce package size, and to improve Power Integrity.
Abstract: Advanced Surface Laminar Circuit (Adv-SLC) is a build-up substrate technology designed to satisfy the requirement of the most advanced semiconductor chips. Adv-SLC is featuring a low Coefficient of Thermal Expansion (CTE) of 10 ppm/degC that reduces the strain in the solder joints and Cu/low-k stacked structure of semiconductor chips during the reflow process, ensures the solder joint reliability, and protects internal delamination of the Cu/low-k stacked structure. This paper describes the power integrity and signal integrity of Adv-SLC and the capability to reduce total layer count with considering X-talk, to reduce package size, and to improve Power Integrity by using Adv-SLC.
01 Jan 2010
TL;DR: In this paper, a photonic crystal power/ground layer (PCPL) is proposed to suppress the power and ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits.
Abstract: Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). In this paper a novel photonic crystal power/ground layer (PCPL) is proposed to efficiently suppress the power/ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits. The PCPL is designed by periodically embedding high dielectric-constant rods into the substrate between the power and ground planes. The PCPL can efficiently suppress the high frequency noise and its radiated EMI generated be the SSN (over 60 dB) with broad stop band bandwidth (totally over 4 GHz below the 10-GHz range, and in the time domain, the P/GBN can be significantly reduced over 90%. The PCPL not only performs good power integrity, but also keeps good signal quality with significant improvement on eye patterns for high-speed signals with via transitions. In addition, the proposed designs perform low radiation of electromagnetic interference caused by the SSN within the stop bands. These extinctive behaviors both in signal integrity and electromagnetic compatibility are demonstrated numerically and experimentally.
Proceedings ArticleDOI
25 Apr 2011
TL;DR: A levelized high-level current model for logic blocks to provide quick current waveform estimation at RTL is proposed and the average peak error of the proposed levelized current model is improved by almost 23% compared to the conventional single-stage current model.
Abstract: Since the power integrity problem has become one of the critical issues that limit the design performance, it is essential to obtain the supply current waveforms at early design stages to make efficient reduction of the supply noise. Therefore, a high-level macro current model is proposed in [11] for logic blocks to provide quick current waveform estimation at RTL. However, due to the different arrival time of internal signals, it is not easy to accurately model the supply current of the whole logic blocks as some fixed templates. Therefore, a levelized high-level current model is proposed in this work for macro blocks. By grouping those gates with similar arrival time as a super-gate, the current waveform of this super-gate can be recorded easily with less error. Then, combining all triangles of every super-gate in time obtains a more accurate supply current waveform, especially for multi-peak cases. In order to consider the different arrival time of different input patterns, a dynamic levelization algorithm is also proposed. As shown in the experimental results, the average peak error of the proposed levelized current model is improved by almost 23% compared to the conventional single-stage current model.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852