Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Modeling of High-frequency Switching Power Noise in Voltage Regulator Module

Abstract: As switching power noise can cause severe power integrity (PI) and signal integrity (SI) problems on printed-circuit-board (PCB), the modeling of DC-DC buck converter, also known as voltage regulator module (VRM), is important for the analysis of noise coupling from the switching power noise induced by VRM to nearby signal and power nets. In this paper, the switching power noise from VRM is analyzed and then classified into two types of noise source, which are dv/dt noise and di/dt noise. The dv/dt noise is modeled by a resonator composed of the RLC series circuit. The di/dt noise is modeled by the inductor current with piecewise linear (PWL) format. The ringing of di/dt noise can be also modeled by the resonator created for the modeling of dv/dt noise. The simulation result proves the power noise generated by the proposed equivalent VRM model presents good agreement with the power noise generated by the HSPICE model of FETs provided by the VR manufacturer. The di/dt noise error ratio is less than 10% and the dv/dt noise error ratio is below 1%.

High-speed GDDRIII System Implementation by Channel Signal and Power Integrity Factorial Design

Abstract: Implementing single-ended Graphic Double Data Rate III (GDDRIII) interface at 1.6 Gbps in production is challenging in the current graphic memory environment. This paper proposes a system design method in the signal and power integrity perspective which could perform the channel factorial electrical analyses to figure out the parameter influence. This methodology could be usefully applied in the budget control and the electrical physical constraint setup on the design phase, and critical parameters could be list down and optimized in the pre-design analysis. We can make a proper compromise among the different design electrical parameters with the corresponding penalties to robustly function up to 1.6 Gbps in the graphic controller data transfer.

A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design

Abstract: Micro bumps and stripes play essential roles for the transmission of signals and the preservation of power integrity in the modern flip-chip packaging process. For different placement block designs on a chip, the best micro bump arrangement and stripe generation method is usually varied accordingly. It often takes a lot of manpower and time cost in generating the delivery path of signal and power transmission in a package. As a result, we propose a way that can automatically generate a power delivery network (PDN) on the top metal layers in a chip and set the coordinate of micro bumps. It can solve the IR drop problem in the early stage, and decrease the integrated circuit (IC) and packaging layout design iteration, thus shorten time-to-market (TTM). Experimental results show that our flows can reduce IR drop to 5% of supply voltage in block.

Computation of power plane pair inductance, measurement of multiple switching current components and switching current measurement for multiple ICs with an island structure

Abstract: The first part of the thesis presents the computation of power / ground plane pair inductance based on Partial Element Equivalent Circuit (PEEC) method in power distribution network (PDN) design. An efficient approach for the inductance computation is investigated. Speed-up techniques are employed include using the faster decay of mutual coupling due to the “differential” currents (same magnitude but opposite directions) in the two planes. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density. The second part presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post dataprocessing procedure is introduced to separate and obtain the parameters of multiple current components. The third part proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure. Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island. Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated. The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage.

An On-Chip Clock Generation Circuit for Smart Catheters

Abstract: Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of −104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.