Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation

Abstract: For the purpose of evaluating the impact of excitation on double data rate (DDR) interface system transmission performance, a methodology for generating the worst-case excitation is proposed for signal integrity (SI) and power integrity (PI) co-simulation. The excitation is produced with the pseudo random bit sequence (PRBS) gated by a square wave of the resonant frequency of the system power distribution network (PDN). The PRBS can reflect non-ideal factors as crosstalk, reflection and loss in the signal line, and the resonant frequency of the PDN can guarantee the maximum simultaneous switching noise (SSN). A data transmission performance simulation environment of currently widely used low power double data rate SDRAM4 (LPDDR4) is constructed based on the advanced I/O buffer information specification Plus (IBIS Plus) model. Compared with the ordinary PRBS excitation, in terms of eye diagrams, the proposed worst-case excitation reduces the eye width and eye height by 4.7% and 19.9%, respectively. Further analysis also proved that 1/2 duty ratio of the gating wave can maximize the influence from the power noise. In conclusion, the proposed worst-case excitation and test environment provide an improved SI/PI co-simulation scenario for the examination of the robustness of DDR system data transmission performance.

Analysis of novel technology for power and signal integrity using a metal particle conductive layer

Abstract: Power integrity (PI) has been an important technological issue in the field of electronic circuits and systems. It has been addressed in important papers using several different approaches [1][2]. The latest concept of the best PI condition is a low impedance between the power and ground lines or planes, that can be maintained regardless of the clock frequency, even in the GHz region. A novel technology was used in our previous study, in which a metal particle conductive layer (MPCL) was used instead of a copper plane [3][4]. This structure improved the PI for any clock frequency, particularly in the GHz region. The MPCLs consist of micrometer sized silver flakes (SF) and binder resin. In this study, we used an epoxy as a binder for conductive paste and polyimide (PI) copper clad laminate (CCL) as the inner dielectric of test coupons. These are general-use material so that they can be made easily, and apply to printed circuit boards (PCBs) and package substrates (PKGs). It has been found from transmission line test coupon measurements, that energy propagation time and frequency characteristics, are strongly affected by the metal particle content and chemical composition. From power/GND plane test coupon measurements, MPCL can reduce Z11 about 70% compared with copper plane from 1 to 5GHz frequency region. In this paper, we reveal the detail phenomena of MPCL exceed the region of usual transmission line theory and some critical factors to improve PI using MPCL.

3D Integration for Wireless Multimedia

Abstract: The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Power-bus noise reduction using ferrite-covered open stub in printed circuit board

Abstract: For suppressing the power-bus resonance at higher frequencies, which causes propagation of electromagnetic noise and detraction of power integrity, we proposed a lossy resonator filter with frequency selectivity and low loss. To suppress noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), a ferrite-covered open stub was formed on a PCB as a lossy resonator filter. Its characteristics were verified by not only full-wave simulation but also measurement using a vector network analyzer. The simulation and measurement results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Through a series of investigations focusing on the input impedance characteristics, this paper clarified that low impedance of the open stub around resonant frequency helps prevent the impedance of the power-ground plane pair from increasing due to parallel plate resonances to achieve power-bus noise reduction.