Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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01 Aug 2012
TL;DR: In this article, a simple and efficient method synthesizing 2D generalized transmission line equations (GTLE) and finite-difference frequency-domain (FDFD) is proposed for power integrity simulation.
Abstract: The numerical simulations of power integrity in electronic packages become more and more significant, which help us to understand the characteristic of power distribution network. In this work, a simple and efficient method synthesizing 2D generalized transmission line equations (GTLE) and finite-difference frequency-domain (FDFD) is proposed for power integrity simulation. The combined method can simulate power/ground plane pair surface mounted with lumped circuit elements such as decoupling capacitor. Several numerical results are presented compared to HFSS. Validation of the proposed method is demonstrated by the results.
01 Jun 2017
TL;DR: This paper presents the nonlinear behavior of the DC-DC Buck converter as EMI generator and two types of switching regimes of the Buck converter: periodic switching and random switching.
Abstract: The Power Distribution Network of a PCB based system is largely influenced by the switching noise from power converters. This paper presents the nonlinear behavior of the DC-DC Buck converter as EMI generator. Time sensitive data collector are based on high speed real time systems which require high quality of power and ground distribution network. By analyzing the interferences generated by the switching noise of the converters there can be made improvements over the Power Integrity of the PCB and overall performance and measurement accuracy of system. In this paper are presented two types of switching regimes of the Buck converter: periodic switching and random switching. A spectral analysis of the output waveform voltage is used to compare both their influence in the system. An experimental model using the Buck converter as noise generator is studied and its behavior influence on the vibroacoustic measurements domain is analyzed. The experimental study will provide useful information for vibroacoustic embedded system designers.
01 Nov 2010
TL;DR: In this article, a practical power integrity simulation method for analyzing EMC performance in design stage is proposed, where a proper countermeasure for any EMC problem can be taken before manufacturing an electric circuit board.
Abstract: Power Integrity(PI) means a quality of the power and ground planes in an electric circuit board. This is closely bound up with the EMC performance of the circuit board. The electric potential actually fluctuates because of the influx of return-current circulating in the power and ground planes, which causes abnormal signals or EMC problems. This paper suggests a practical PI simulation method for analyzing EMC performance in design stage. With using this method, a proper countermeasure for any EMC problem can be taken before manufacturing an electric circuit board
26 Jul 2021
TL;DR: In this paper, the authors analyzed the impact of errors in ESL on power distribution network (PDN) impedance using measurements and simulations and demonstrated the dependence of ESL on the layout of capacitors.
Abstract: While the equivalent series inductance (ESL) of multi-layer ceramic capacitors is widely used for power integrity analysis, the definition of ESL is ambiguous. Its value depends on how the capacitor is mounted on the PCB and on coupling to the nearby pads, traces, vias, and return plane. A single value for ESL is not sufficient to quantify the behavior of a capacitor in a broad number of power distribution network (PDN) designs and will lead to errors in the simulated PDN impedance. The impact of errors in ESL is analyzed in the following paper using measurements and simulations. The dependence of ESL on the layout is demonstrated using full-wave simulations. Measurements of 0402 and 0201 capacitors show that using the datasheet ESL can lead to up to 47% overestimation of the value of the total connection inductance, L above . Test PDN structures with various stackups were analyzed to quatify the error in the total impedance due to errors in ESL. Results show that errors in ESL can lead to a 26% overestimation in the overall PDN impedance in the studied examples. Overestimation of ESL may cause more capacitors to be put on the board than needed.
TL;DR: In this paper , the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks, are outlined, with a focus on protecting against physical implementations attacks.
Abstract: Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.