Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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20 Apr 2011TL;DR: In this paper, the authors describe how to characterize the power distribution network and how to correlate the measurement data and simulation data to realize better power integrity (PI) design, which can supply stable source voltage even if source current changes due to operation of ICs.
Abstract: Power Integrity (PI) is a popular topic in today's electronic equipment industry because recent electric equipment uses various ICs, ex. Microprocessor, Memory, FPGA and ASIC. In addition, PI typically has lower source voltage and larger current required. To realize robust design, better power distribution network (PDN) is required. Good PDN means it can supply stable source voltage even if source current changes due to operation of ICs. It requires lower impedance characteristics of PDN from ICs. This paper describes how to characterize the PDN and how to correlate the measurement data and simulation data to realize better PI design.
22 Nov 2010
TL;DR: A novel integral equation method for analysis of the power integrities in power distribution networks is presented and the accuracy and efficiency of the proposed method is verified.
Abstract: A novel integral equation method for analysis of the power integrities in power distribution networks is presented in this paper. The electromagnetic field inside the power distribution network is expressed in the modal field distribution. The modal field is then expressed by using the Dyadic Green's functions. Integral equations are created for these modes. During the discritization of the integral equations, network ports are defined between the power-ground planes. Their equivalent networks are extracted through the moments method solution of the integral equations. This circuit model can be used for the signal and power integrities analysis. Through numerical examples, the accuracy and efficiency of the proposed method is verified.
01 Oct 2019
TL;DR: A fast finite element assembling method for power network DC integrity checks of PCBs is proposed and the resulting FEM solver leads to 3X speed over a commercial power integrity solver with no more than 0.7% errors.
Abstract: Power integrity analysis is of great significance in the field of circuit design, especially the design of modern high speed circuit system. For the high performance printed circuit boards (PCBs) and IC design, power delivery network DC integrity checks play an important role. However, the element assembling process in finite element method (FEM) can take significant portion of total computing time. In this paper, a fast finite element assembling method for power network DC integrity checks of PCBs is proposed. We divided the mesh into a serious of bins and elements in different bins could be assembled in parallel. Further more, a dynamic circle shape approximation method is introduced to further control the number of elements due to vias and circular objectives. As a result, the new solver can easily perform progressive trade off between speed and accuracy. Experimental results of two PCB examples on a 3.6-GHz Intel i7 Dual-core CPU show that the proposed multi-thread assembling method can achieve 2X speedup over existing single-thread assembling methods. A dynamic circle shape approximation method is introduced to further control the number of elements and speed up the solver process. The resulting FEM solver leads to 3X speed over a commercial power integrity solver with no more than 0.7% errors.
05 Dec 2011
TL;DR: A way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches by defining of amount of CMOS devices simultaneously toggling at the same place and following voltage droop analysis.
Abstract: Proposed a way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches. It includes defining of amount of CMOS devices (in the same cluster) simultaneously toggling at the same place and following voltage droop analysis of whether amount of devices, belonging to the same cluster, toggle above the predefined threshold, all over the functional pattern(s). Additionally, we define clear guidelines to the implementation tools how constantly toggling CMOS devices like clock buffers, are expected to be placed in order to avoid PDN failures. Some examples of the proposed approach are provided.
17 Nov 2009
TL;DR: In this paper, a perforated disk resonator with non-plated holes was used to investigate the BIE and effective dielectric medium approaches for common via array structures.
Abstract: In high-speed printed circuit board (PCB) designs, vias play a critical role in determining signal and power integrity. This paper uses disk resonators to investigate modeling approaches for common via array structures. Boundary integral equation (BIE) and effective dielectric medium approaches are used for a perforated disk resonator with non-plated holes, using dielectric properties derived from a solid disk resonator study. Both approaches are compared and validated with measurements.