Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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Dissertation•
01 Jan 2010
TL;DR: In this article, the degradation of power affects the timing closure of the AVR processor, thus affecting the performance, and the first overshoot after voltage drop increases for wider metal wires compared to lesser width of metal wires.
Abstract: In the deep submicron era, the power supply voltage to the logic devices should be well
within the bound limits. The degradation of power affects the timing closure of the
chip, thus affecting the performance. In this thesis, the analysis flow used in previous
study is modified to make it generic to all series of AVR processors. By extracting a
power grid model and subjecting it to extensive simulations, the issue causing the
power degradation is analysed. Analysis results show that the cause for the first
voltage drop is due to two factors, that is, current loads and resistive property of the
metal wires. The first overshoot after voltage drop increases for wider metal wires
compared to lesser width of metal wires. Nodes of the power grid having large voltage
drop show that on-chip self inductance can no longer be ignored in designing power
distribution networks for high frequency circuits.
01 Jul 2018
TL;DR: In this paper, the authors provide a simple method for estimating the required decoupling C for flat impedance and demonstrate the adverse effect of inductance in the PDN that requires an increase in the required total decoupled capacitance.
Abstract: Power integrity applications suffer from the inability to precisely define the dynamic transient current. This has led to an increased interest in designing for a target impedance over a wide spectral bandwidth. Prior art has shown that a flat impedance design results in the lowest m V ripple excursion per Amp of step load. [1] This paper provides a simple method for estimating the required decoupling C for flat impedance. This method is then used to demonstrate the adverse effect of inductance in the PDN that requires an increase in the required total decoupling capacitance.
27 May 2014
TL;DR: This paper has demonstrated design success of stretched LPDDR3 up to 2.133Gbps by applying rigorous design optimization based on comprehensive PI-aware SI analysis which includes signal quality improvement and power delivery optimization.
Abstract: Recent fast-evolving mobile system demands high bandwidth and low power consumption, necessitating extension of LPDDR3 beyond 1.6 Gbps. This demand, however, brings significant technical challenges from the perspective of signal and power integrity. A simple way of mitigating signal integrity issue at the challenging speed is to use ODT (On-Die Termination). Since ODT significantly increase power consumption, the use of ODT is not an attractive solution in a mobile system which considers low power consumption as primary metric. Thus, comprehensive design optimization with given design constraint is a practical solution which can avoid penalty of power consumption in the mobile system. In this paper, we have demonstrated design success of stretched LPDDR3 up to 2.133Gbps by applying rigorous design optimization based on comprehensive PI-aware SI analysis. It includes signal quality improvement and power delivery optimization. The Both metrics are organically considered during optimization process to achieve successful system operation up to 2.133Gbps without additional power consumption by ODT use.
TL;DR: This paper proposed an efficient and scalable framework for the worst-case power integrity prediction, which can handle general tasks including dynamic noise prediction and bump current prediction, and first reduces the spatial and temporal redundancy in the PDN and input current vector, and then employs efficient feature extraction as well as a novel convolutional neural network architecture to predict theworst- case power integrity.
Abstract: Power integrity analysis is an essential step in PDN sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-consuming to conduct full-stack PDN simulation to check the power integrity for different test vectors. Recently, various works have proposed machine learning based methods for PDN power integrity prediction, many of which still suffer from large training overhead, inefficiency, or non-scalability. Thus, this paper proposed an efficient and scalable framework for the worst-case power integrity prediction, which can handle general tasks including dynamic noise prediction and bump current prediction. The framework first reduces the spatial and temporal redundancy in the PDN and input current vector, and then employs efficient feature extraction as well as a novel convolutional neural network architecture to predict the worst-case power integrity. Experimental results show that the proposed framework consistently outperforms the commercial tool and the state-of-the-art machine learning method with only 0.63-1.02% mean relative error and 25-69 × speedup for noise prediction and 0.22-1.06% mean relative error and 24-64 × speedup for bump current prediction.
TL;DR: In this paper , a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level is presented by exploiting a multi-stage macromodeling and compression process, leading to a compact representation of the system dynamics in terms of a linearized state-space structure with multiple feedback loops from the FIVR controllers.
Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference structure is a complete power distribution network (PDN) from platform voltage regulator module (VRM) to multiple cores, including board, package, decoupling capacitors, and per-core fully integrated voltage regulators (FIVR). All blocks are characterized and known through high-fidelity models derived from first-principle solvers (full-wave electromagnetic and circuit-level extractions). The complexity of such detailed characterization grows very large and becomes intractable, especially for power integrity verification of massive multicore platforms subjected to real workload scenarios. We approach this problem by exploiting a multi-stage macromodeling and compression process, leading to a compact representation of the system dynamics in terms of a linearized state-space structure with multiple feedback loops from the FIVR controllers. The PDN macromodel is obtained through a data-driven approach starting from reference small-signal frequency responses, obtaining a sparse and structured representation specifically designed to match the behavior of the reference system. The resulting compact model is then solved in time-domain very efficiently. Results on mobile and enterprise server benchmarks demonstrate a speedup in runtime up to 50× with respect to HSPICE, with negligible loss of accuracy.