Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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10 Aug 2022
TL;DR: In this article , an innovative substrate design scheme is proposed to optimize the substrate design with the lowest coupled noise based on the frequency domain impedance analysis of the power distribution network, thereby improving the power integrity of the product.
Abstract: As increasingly high demand on system integration and performance, system in package (SIP) has become one of the mainstream packaging forms in a scalable and cost-effective way. However, the number of chips and stacked layers increase, resulting in increasingly prominent power integrity issues. Compared to PCB design, PI optimization strategies for package substrate are limited. In this paper, an innovative substrate design scheme is proposed to optimize the substrate design with the lowest coupled noise based on the frequency domain impedance analysis of the power distribution network, thereby improving the power integrity of the product.
05 Feb 2015
TL;DR: The proposed scheme reduces the coupling effect of noise on differential nodes at Sense Amplifier by decoupling the differential nodes from power supply noise using highly capacitive shared reference lines and results in improvement in speed and power by 20% and 5% respectively with no area loss.
Abstract: On-chip power grid design is a major challenge in submicron technologies. High peak current coupled with inductive reactance of supply mesh results in power integrity issue results in ringing. This supply noise reduces the available differential voltage for sensing and results in read failure in Read only memory (ROM). Controlling the noise by using large decoupling capacitor is area consuming. Proposed scheme uses a noise tolerant reference generation. Scheme reduces the coupling effect of noise on differential nodes at Sense Amplifier. This is done by decoupling the differential nodes from power supply noise using highly capacitive shared reference lines. Thus, the impact of supply noise on differential voltage is reduced by a#x007E;90%. Scheme results in improvement in speed and power by 20% and 5% respectively with no area loss. We achieved 50MHz operating frequency with 8T-NAND High VT (HVT) ROM for 8192x128 (i.e. 8K words and 128 bits) instance.
06 Mar 2014
TL;DR: This DDR3 memory I/F design addresses the external environment requirements, especially relating to power integrity, and achieves 2.667Gb/s operation in a wirebond package and singleside mounted PCB.
Abstract: DDR3 memory interface (I/F) with single-end signals is very sensitive to external environments, such as chip package type and system board design. In order to guarantee the system performance, IP providers often define the package and PCB design constraints to reduce product risks [1]. These design constraints may increase the package size and DDR3 PCB area to cost, increasing the whole system cost. Therefore, our DDR3 memory I/F design addresses this problem, relaxing the external environment requirements, especially relating to power integrity, and achieves 2.667Gb/s operation in a wirebond package and singleside mounted PCB. The difference between double-side and single-side mounted PCB is shown in Fig. 26.6.1. The capacitor on the PCB cannot be mounted directly near the SOC on the back side of PCB. This external environment increases the distance of the current return loop and also increases the inductance of power decouple capacitance equivalently.
DOI•
01 Aug 2021TL;DR: In this article, a 3D finite element method full-wave solver is introduced for the interconnect model extraction for printed circuit boards, packages, and integrated circuits, and a massively parallel computational framework is designed to address the issue of capacity and scalability due to the increase in system size and complexity.
Abstract: A 3D finite element method full-wave solver is introduced. It has been successfully applied for the interconnect model extraction for printed circuit boards, packages, and integrated circuits. A massively parallel computational framework is designed to address the issue of capacity and scalability due to the increase in system size and complexity. In addition, the method of field-circuit co-simulation is discussed, and it is critical to real-world signal integrity and power integrity applications.
31 Dec 2012
TL;DR: In this article, the authors experimentally verified the package-common-mode resonance by comparing scattering parameters with variation of CMOS output jitter, in order to suppress increase of the jitter.
Abstract: When an LSI package is mounted on a PCB, parasitic couplings are unintentionally generated between them. Antiresonance of these couplings (package-common-mode resonance) can cause degradation of signal and power integrity. In this paper, the authors experimentally verified the package-common-mode resonance by comparing scattering parameters with variation of CMOS output jitter. In order to suppress increase of the jitter, resister-dumping method was tested as a countermeasure.