Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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27 Mar 2006
TL;DR: Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening of signal-integrity and power-Integrity in a case where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts.
Abstract: Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters.
14 citations
TL;DR: In this article, the authors presented a systematic macromodeling of power-bus structures based on the cavity model, where more accurate models were used to describe conductor and dielectric losses, thus improving accuracy at low frequencies.
Abstract: With increased operating frequencies and circuit component density, signal and power integrity problems caused by voltage bounces have become more important for high-speed digital systems. This paper presents a systematic macromodeling of power-bus structures based on the cavity model: first, more accurate models are used to describe conductor and dielectric losses, thus improving accuracy at low frequencies; second, a rational model of the overall power/ground structure in the Laplace domain is presented, and third, the rational macromodel is used to identify the dominant poles, and a simplified SPICE-compatible equivalent circuit is synthesized by using only the selected poles. The numerical results confirm the correctness and effectiveness of the method.
14 citations
20 Apr 2009
TL;DR: This work investigates the impact of power rail noise on EMI, and shows that by limiting this noise source it is possible to drastically reduce the conducted emissions and presents a transistor-level lumped-element simulation model of the system power distribution network (PDN).
Abstract: In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.
14 citations
03 Oct 2005
TL;DR: In this paper, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool and the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method, with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach.
Abstract: The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on PCB's. In fact, providing the required power to the different IC's at the specified noise-free voltage levels allows a correct functioning of the overall PCB systems. More over, the ongoing trend of replacing active devices with peripherally located I/O and PWR/GND pins with areally located I/O and PWR/GND pins (BGA packaged) increases the complexity of the models, when power delivery issues need to be studied in a larger contest, such as the overall PCB's. The employment of the powerful, but simple, concept of the segmentation method allows investigation of the power delivery network of the PCB systems in two fundamental stages. During the first stage, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool. During the second stage the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method, with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach
14 citations
09 Apr 2006
TL;DR: This paper shows that using impedance as constraints leads to large overdesign and then develops a noise driven optimization algorithm for decoupling capacitors in packages for power integrity that reduces the decoupled capacitor cost by 3x and is also more than 10x faster even with explicit noise computation.
Abstract: The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to large overdesign and then develop a noise driven optimization algorithm for decoupling capacitors in packages for power integrity. Our algorithm uses the simulated annealing algorithm to minimize the total cost of decoupling capacitors under the constraints of a worst case noise. The key enabler for efficient optimization is an incremental worst-case noise computation based on FFT over incremental impedance matrix evaluation. Compared to the existing impedance based approaches, our algorithm reduces the decoupling capacitor cost by 3x and is also more than 10x faster even with explicit noise computation.
13 citations