Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory

Abstract: The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.

New Multiport I/O Model for Power-Aware Signal Integrity Analysis

Abstract: This paper presents a new multiport power-aware behavioral model formulation and extraction for high-speed input/output (I/O) buffers that enable the transient prediction of power and ground bouncing effects under simultaneously switching output (SSO) buffers for signal and power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the I/O buffer information specification (IBIS) buffer issue resolution documents (BIRDs) (i.e., BIRD-95.6 and BIRD-98.3) and the macromodeling via parametric identification of logic gates (Mpilog) (i.e., artificial neural network). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation that integrates both the previous BIRDs with a well-designed characterization and parametric extraction procedure. The accuracy and computational performances of the proposed model is evaluated under a realistic SSO scenario.

Evolution of organic chip packaging technology for high speed applications

Abstract: The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

A Novel System-Level Power Integrity Transient Analysis Methodology using Simplified CPM Model, Physics-based Equivalent Circuit PDN Model and Small Signal VRM Model

Abstract: The goal of a well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise and errors delivered to chip. This paper provides power integrity engineers a guideline to model PDN agilely in a simplified method and choose specific voltage regulator module model under specific circumstances. These comparisons and studies present the advantage of this novel methodology using equivalent circuit model for system level power integrity transient analysis.

An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

Abstract: As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was developed by IBM is better suited for I/O increase than the typical peripheral wire-bond design. One of the most important characteristics of flip-chip designs is that the I/O buffers could be placed anywhere inside a chip, just like core cells. Motivated by [14] in proposing various I/O planning constraints, we develop a block and I/O buffer placement method in wirelength and signal skew optimization (especially for differential pair signals), and power integrity awareness for chip-package codesign. The results have shown that our approach takes care of power integrity and outperforms [12] in weighted performance metrics optimization.