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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings ArticleDOI
01 Nov 2010
TL;DR: A prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken, and a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design.
Abstract: Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

12 citations

Proceedings ArticleDOI
W. T. Chen1, C. C. Lin1, C.H. Tsai1, H. Hsia1, Kai-Yuan Ting1, Shang-Yun Hou1, C. T. Wang1, Douglas Yu1 
03 Jun 2020
TL;DR: These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.
Abstract: A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm2 and low leakage current of <1 fA/μm2. The impact of the DTC on power integrity of the logic-HBM2E system is investigated. In the logic core area, the system power delivery network (PDN) impedance and the 1st voltage droop for the CoWoS with the DTC are 93% and 72% lower than those without the DTC. For the HBM2E PHY area, the PDN impedance and simultaneously switching noise (SSN) of VDDQ for the CoWoS with the DTC are 76% and 62% lower than those without the DTC. Moreover, 11.2% and 16.6% unit interval (UI) eye margin are obtained at the data rate of 2.8 and 3.2 Gbps, respectively. These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.

12 citations

Proceedings ArticleDOI
10 Oct 2011
TL;DR: In this paper, a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies is presented, where a lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current.
Abstract: This paper presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post data-processing procedure is introduced to separate and obtain the parameters of multiple current components. The results obtained by the proposed method are validated with other approaches.

11 citations

Proceedings ArticleDOI
01 Oct 2014
TL;DR: In this paper, an improved plane-pair model for power distribution system modeling using the partial element equivalent circuit approach is presented, where the modified nodal analysis with a submeshing strategy leads to an efficient and accurate circuit solution in both the frequency domain and time domain.
Abstract: In this paper, we present an improved plane-pair model for power distribution system modeling using the partial element equivalent circuit approach. The modified nodal analysis with a sub-meshing strategy leads to an efficient and accurate circuit solution in both the frequency domain and time domain.

11 citations

Proceedings ArticleDOI
01 Jul 2018
TL;DR: The main novel contribution of this work is the formulation of the model fitting equations in a decoupled form, which allows for a very efficient implementation in case of interconnects with a large number of interface ports, as typically required in Signal and Power Integrity applications.
Abstract: This paper introduces an algorithm for the construction of reduced-order macromodels of electrical interconnects starting from their sampled scattering responses. The produced macromodels embed in a closed-form an approximate dependence of the model equations on external parameters such as geometrical dimensions or material characteristics. The resulting parameterized models are easily cast as parameter-dependent SPICE netlists, which can be used for system-level Signal and Power Integrity assessment via numerical simulation, including sensitivity and optimization tasks. The main novel contribution of this work is the formulation of the model fitting equations in a decoupled form, which allows for a very efficient implementation in case of interconnects with a large number of interface ports, as typically required in Signal and Power Integrity applications. The parameterized models are guaranteed stable and passive for any configuration of the external parameters, thus ensuring stable transient numerical simulations.

11 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852