Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Analysis of Complete Power-Distribution Network and Co-Design Optimization

Abstract: This paper describes the modelling analysis for a power-distribution network and demonstrates co-design and co-simulation in using the detailed prototype model, which includes a chip, package, and printed circuit board. A circuit simulator and a 2D solver using the finite element method are used to study the frequency and transient responses for the core switching noise. In the model, we assume a chip model (current profile and on-chip capacitance) and define the circuit parameters with an equivalent circuit to meet the target impedance. Then the physical design of the package and printed circuit board were done to check all of the required circuit parameters. According to the modelling and evaluation, the package design with a low equivalent series inductance capacitor in the bottom layer and a thin core structure is more advantageous than a capacitor in the top layer.

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network

Abstract: In this paper, an efficient parallel flow for the design of the full power distribution network (PDN) is proposed. The analysis demonstrates the impact of the voltage regulator model in both frequency and time domain response. Based on the experimental results, it is observed that including the voltage regulator model in the PDN model increases the transient voltage drop and PDN response which need to be considered for nanoscale ICs. The flow is optimized using parallel processing to speedup slow response simulation time of the off chip voltage regulator. The study highlights the power integrity issues related to voltage regulator in broadband frequency ranges. The experimental results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors compared to HSPICE and other commercial simulators. The PDN simulation time is reduced from hours to less than a minute.

Selecting Surrogate-Based Modeling Techniques for Power Integrity Analysis

Abstract: In recent years, extensive usage of simulated power integrity (PI) models to predict the behavior of power delivery networks (PDN) on a chip has become more relevant. Predicting adequate performance against power consumption can yield to either cheap or costly design solutions. Since PI simulations including high-frequency effects are becoming more and more computationally complex and expensive, it is critical to develop reliable and fast models to understand system’s behavior to accelerate decision making during design stages. Hence, metamodeling techniques can help to overcome this challenge. In this work, a comparative study between different surrogate modeling techniques as applied to PI analysis is described. We model and analyze a PDN that includes two different power domains and a combination of remote sense resistors for communication and storage CPU applications. We aim at developing reliable and fast coarse models to make trade off decisions while complying with voltage levels and power consumption requirements.

Signal and power integrity design of 2.5D HBM (High bandwidth memory module) on SI interposer

Abstract: Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

System level signal and power integrity analysis for 3200Mbps DDR4 interface

Abstract: For single-ended signaling DDR4 channels at 3200Mbps, signal and power integrity issues become increasingly challenging with much smaller voltage and timing windows to balance the budget. As systems increase data rate and IO count, supply noise does not scale accordingly. We present a system level signal and power co-simulation analysis to optimize system performance under stringent timing requirement [1]. Signal integrity of DDR4 interface, such as inter-symbol interference ISI, reflection, and signal cross talk, needs to be minimized in order to meet an ever shrinking timing budget. Also, power delivery network (PDN) design becomes very difficult as a result of smaller die size and multilayer complex package design. SI and PI co-design optimization is driven by both channel performance and overall system cost.