scispace - formally typeset
Search or ask a question
Topic

Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


Papers
More filters
Proceedings ArticleDOI
08 May 2016
TL;DR: This paper presents a novel iterative method for finding an equivalent set of poles and residues of a system from its discrete frequency domain response, and has extensive applications in the modeling and simulation of signal and power integrity structures.
Abstract: Frequency-domain modeling and simulation of systems is performed widely today; however, time-domain transient simulation of systems often requires synthesis of network S/Y/Z-Parameters as lumped equivalent circuits. In turn, circuit synthesis requires determination of the set of poles and residues implied by the network parameters. This paper presents a novel iterative method for finding an equivalent set of poles and residues of a system from its discrete frequency domain response. Each iteration chooses up to 3 consecutive samples from the given response to find a local fit; such iterations are repeated until the sum of all local fits matches the given response within a specified target error, across the entire designated bandwidth. The proposed method is demonstrated for two test cases: 1) microstrip and 2) power planes. PRESS has extensive applications in the modeling and simulation of signal and power integrity structures; such as, high-speed signal and power delivery interconnect networks of electronic packages and printed circuit boards.

10 citations

Proceedings ArticleDOI
26 May 2015
TL;DR: In this article, the authors studied the performance of the Fan-out-based system-in-package (SiP) module with dual-layer RDL in terms of RF impedance matching, power integrity and thermal distribution with complete SiP module.
Abstract: The purpose of this paper is to study the Wi-Fi SiP (System-in-Package) module manufactured by the Fan-out technology, which includes dual layer RDL. In this Fan-out package, numerous components (including active chip and RLC passive components) are encapsulated by compression molding, and signals are interconnected by RDL. Without substrate (replaced by molding compound), this Fan-out package can be thinner and lower cost. Electrical simulation for RF signal integrity is also studied in this paper, to understand the Fan-out technology's characterization on RF SiP design application. To evaluate the Fan-out technology on module level performance, simulation on RF impedance matching, power integrity and thermal distribution with complete Wi-Fi SiP module is also discussed in this paper.

10 citations

Proceedings ArticleDOI
18 Nov 2008
TL;DR: An integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise.
Abstract: Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.

10 citations

01 Jan 2007
TL;DR: In this paper, the authors describe the design trade-offs made for the Altera Stratix III family of FPGAs to achieve performance while maintaining costs and measured data on design prototypes as well as simulation predictions.
Abstract: FPGAs have traditionally been optimized for low-cost environments where signal and power integrity are minor considerations. With today’s requirements for high-speed memory and serial interfaces, FPGA silicon and packages must be designed to provide good signal and power integrity while still maintaining cost objectives. Performance goals for nearand far-end simultaneous switch noise (SSN) noise as well as power supply quality are the primary metrics. Both nearand far-end noise is generated when all drivers switch concurrently creating SSN. Mutual coupling from aggressor signals to victims and delta-I noise associated with the inductance of power and ground paths are the primary mechanisms that cause noise during the rise time of the aggressors. The di/dt of the aggressors is responsible for this noise. Both horizontal structures (transmission lines and planes) and vertical structures (bumps, balls, and vias) contribute to SSN crosstalk. The vertical structures are responsible for most of the noise. Neither nearnor far-end noise should exceed 50 percent of the signal noise margin. This goal is achieved by controlling the signal I/O to power and ground ratios. The quality of the power supply, seen by the circuits on the die, is important for proper circuit performance and the ability to meet timing and jitter specifications. The power distribution network (PDN) for the package die combination is an important consideration in determining power supply quality. Through the use of on-package decoupling (OPD) capacitance and on-die capacitance (ODC), the power supply voltage tolerance is held to +/-10 percent of nominal throughout the difficult die/package resonance frequency band. This paper describes the design trade-offs made for the Altera Stratix III family of FPGAs to achieve performance while maintaining costs. Measured data on design prototypes as well as simulation predictions are presented.

10 citations

Proceedings ArticleDOI
27 May 2008
TL;DR: In this article, the impact of standard and coreless packages on the overall high-speed system performance for data rate beyond 20 Gbps was analyzed by employing statistical system simulation methods, and the package impact on the system performance metrics such as voltage and timing margins and bit error rate (BER) bathtub curves in both time and voltage was analyzed.
Abstract: This paper analyzes the impact of standard and coreless packages on the overall high-speed system performance for data rate beyond 20 Gbps. Instead of focusing on package electrical performance in isolation, we study the package impact on the system performance metrics such as voltage and timing margins and bit error rate (BER) bathtub curves in both time and voltage by employing statistical system simulation methods. Furthermore, the package impact on the quality of the power supply network is also studied using conventional frequency and time domain simulation techniques. Finally, three designs with standard and coreless packages are analyzed to compare the package impacts on signal integrity and power integrity of high-speed systems.

10 citations


Network Information
Related Topics (5)
Integrated circuit
82.7K papers, 1M citations
80% related
Antenna measurement
39.6K papers, 494.4K citations
78% related
Antenna (radio)
208K papers, 1.8M citations
77% related
CMOS
81.3K papers, 1.1M citations
77% related
Dipole antenna
38K papers, 513.8K citations
77% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852