Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity

Abstract: Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

Signal integrity: Efficient, physics-based via modeling: Principles and methods

Abstract: This article discusses the high-frequency behavior of thru-hole vias enclosed by solid reference planes in packages and printed circuit boards and reviews some efficient modeling alternatives for signal and power integrity applications. The electromagnetic behavior of vias, including the excitation of parallel-plate modes and the role of return vias, is introduced as preamble to the modeling approaches. The physics-based via model and its building blocks are then discussed. The last section reviews some improvements to the via model, covering intrinsic models for the near field of vias and the utilization of contour integral and multiple scattering methods.

Low crosstalk simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver

Abstract: We developed high-density silicon-photonics multichannel receiver and demonstrated 12ch × 25 Gb/s error-free operations at the bit-error-rate of < 1E-12 for the pseudo random binary sequence (PRBS) of 231−1 signals. Carefully designed high power integrity successfully led to very small crosstalk penalty of 1.2 dB under the simultaneous operation at all 12 channels.

Controllable parameters identification for high speed channel through signal-power integrity combined analysis

Abstract: The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip power delivery network (PDN) effectiveness, and including the power delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.

Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification

Abstract: This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructed with standard cells, and thus can be easily embedded in SoCs for design verification. The performance of the gated oscillator is verified with fabricated test chips in a 90 nm process.