Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Development of a practical electro-magnetic interference (EMI) simulation in high speed optical transceivers

Abstract: The growing bandwidth of optical communication systems has made great improvements to information technology infrastructures. However, electro-magnetic compatibility becomes an issue due to the high frequency of the components. EMI problems occur due to the miniaturization and high density of the Printed Circuit Board (PCB) mounted on the system. Generally, electro-magnetic radiation is generated by the circuit elements. For example, switching in the LSI raises the voltage swing between the power source and ground which is known as “ground bounce”. EMI problems related to the ground and power source are linked to the power integrity, and is influenced by the structure of the patch antenna parasitically existing between the power source and ground. That is to say, most of the time this problem can be solved by utilizing the appropriate power source and ground pattern layout at the PCB design stage. However, high speed digital signals measuring at more than 10 Gigabit per second (Gbit/s) typically have high frequency components in excess of 40GHz. There is little feasible knowledge available that illustrates guidelines for the perfect layout method to prevent the emission on the PCB for such a high frequency application. Therefore, we focused on the Finite Element Method used in the 3D electromagnetic field analysis simulator so that we could solve the emission within the frequency domain. We first correlated both qualitatively and quantitatively the actual measurements and the simulation results. Then we investigated the countermeasure for the emission intensity (EMI level) from the 10 Gbit/s optical transceiver by simulation and then verified it.

Parallel Plate Impedance and Equivalent Inductance Extraction Considering Proximity Effect by a Modal Approach

Abstract: A modal approach for parallel plate impedance and equivalent inductance extraction for power integrity analysis including ball grid arrays (BGAs) between two parallel plates is presented. Since the BGAs are placed close to each other, the current flowing through each ball is not uniformly distributed due to the proximity effect. In this paper, a modal-based cavity method is proposed to count for this proximity effect. Analytical solutions for both the parallel plate impedance and the equivalent inductances associated with the BGAs are derived from the modal-based cavity method. The proposed method is validated by finite element method simulations and the application of the proposed method for power distribution network design is demonstrated.

Novel RDL Design of Wafer-Level Packaging for Signal/Power Integrity in LPDDR4 Application

Abstract: The emerging wafer-level packaging (WLP) technology suffers from serious signal integrity (SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious parasitic effects by the high-density RDL traces and less flexibility of decoupling capacitors, so the robust power distribution network is critical to design. This paper proposed a novel two-layered RDL design in low-power double data rate fourth generation (LPDDR4) application by proposing a novel power/ground meshed layout for superior PI performance. Besides, the second-order RLC simplified model and normalized resistance are derived to handle the process scaling issue for successful SI by adjusting the cross-sectional structure of RDL so that LPDDR4 4266 can work well on 2- $\mu \text{m}$ WLP.

Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks

Abstract: Enhancing signal integrity (SI) and reliability in modern computer platforms heavily depends on the post-silicon validation of high-speed input/output (HSIO) links, which implies a physical layer (PHY) tuning process where equalization techniques are employed. On the other hand, the interaction between SI and power delivery networks (PDN) is becoming crucial in the computer industry, imposing the need of computationally expensive models to also ensure power integrity (PI). In this paper, surrogate-based optimization (SBO) methods, including space mapping (SM), are applied to efficiently tune equalizers in HSIO links using lab measurements on industrial post-silicon validation platforms, speeding up the PHY tuning process while enhancing eye diagram margins. Two HSIO interfaces illustrate the proposed SBO/SM techniques: USB3 Gen 1 and SATA Gen 3. Additionally, a methodology based on parameter extraction is described to develop fast PDN lumped models for low-cost SI-PI co-simulation; a dual data rate (DDR) memory sub-system illustrates this methodology. Finally, we describe a surrogate modeling methodology for efficient PDN optimization, comparing several machine learning techniques; a PDN voltage regulator with dual power rail remote sensing illustrates this last methodology.

Power integrity simulation of power delivery network system

Abstract: As a result of the increasing operating frequency and the number of transistors of IC, not only the signal integrity (SI), but the power integrity (PI) has also grown from non-existent to an important system. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE®. The accuracy of the simulation results are also compared with the measurement results.