Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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24 Mar 2014
TL;DR: This work proposes a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the Power/Ground (P/G) Through-Silicon-Vias (TSVs) by optimizing the P/G TSV placement and shows that the average IR-drop can be reduced using the proposed method compared to a random placement technique with a much smaller runtime.
Abstract: In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design due to the increasing power density and larger supply current compared to 2D-ICs. As an important part of 3D-IC PDNs, Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be well-managed. Excessive or ill-placed P/G TSVs impact the power integrity (e.g. IR-drop), and also consume a considerable amount of chip real estate. In this work, we propose a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the P/G TSVs. The goal of our approach is to minimize the average IR-drop while satisfying the total area constraint of TSVs by optimizing the P/G TSV placement. Therefore, the locations, sizes and the total number of the P/G TSVs are co-optimized simultaneously. The experimental results show that the average IR-drop can be reduced by 11.8 % in average using the proposed method compared to a random placement technique with a much smaller runtime.
7 citations
TL;DR: This work presents a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints that can reduce the power network area by 19.4% on average under the same signal and power integrity constraints with better routing quality, but use less runtime.
7 citations
TL;DR: The authors focus on efficient analysis and design strategies for reliable RF boards dedicated to integrity monitoring of ICs based on an EM/circuit co-design technique that demonstrates their validity and efficiency for analysis, deembedding and design purposes.
Abstract: At the moment a lot of attention is devoted to power integrity (PI), signal integrity (SI) and electromagnetic compatibility (EMC) of integrated circuits (ICs). For PI-, SI- and EMC-aware design, the modelling and characterisation of ICs is indispensable. Nevertheless, measuring the performance of ICs is not straightforward. Often, the behaviour of the IC-under-test is characterised by placing it on a radio frequency (RF) board and by performing measurements on the board. It was observed that this board often influences the characterisation of the IC. In this study the authors focus on efficient analysis and design strategies for reliable RF boards dedicated to integrity monitoring of ICs. The approach presented here is based on an EM/circuit co-design technique. The authors apply the technique to a canonical test board used for, among others, conducted susceptibility testing of ICs up to a frequency of 2.5 GHz. This is considered to be a relatively high frequency for conducted susceptibility testing of ICs, having the advantage of incorporating the important 2.45 GHz Industrial, Scientific and Medical band. Simulation results illustrate the novel techniques and demonstrate their validity and efficiency for analysis, deembedding and design purposes.
7 citations
19 May 2008
TL;DR: In this article, an integrated signal integrity analysis method which comprises the interaction among power networks, signal operations, and circuit structures of the full system is introduced, which is an effective leverage to determine the performance of the system before manufacturing.
Abstract: Analysis of signal integrity and power integrity are very important to fill the gap between the high performance and the low cost of the DTV system including chip, package and board. In this paper, an integrated signal integrity analysis method which comprises the interaction among power networks, signal operations, and circuit structures of the full system is introduced. The experimental results present excellent correlation between the measurement and results of simulations. The proposed approach is an effective leverage to determine the performance of the system before manufacturing.
7 citations
01 Jan 2011
TL;DR: A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance and Taguchi array optimization has been applied during the optimization process.
Abstract: System level signal integrity and power integrity problems for high speed serial links have been explored in this paper. An example of the USB 2.0 IP has been used in this paper, but the analysis is generic for all serial links. This paper considers signal and power integrity as effects simultaneoulsy. A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance. Sensitivity analysis is carried out with a set of dependent parameters affecting the performance. Taguchi array optimization has been applied during the optimization process. Finally, reflection gain concept is also applied to further improve the performance for the eye diagram. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc. Index Terms—Signal integrity, power integrity, serial links, bit error rate (BER), high speed data transmission
7 citations