Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Robust optimization of serial link system for signal integrity and power integrity

Abstract: Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK taking into account the external parameters like board, package, measurement environment which influence the performance of the channel. Parameters variations appearing from manufactura-bility constraints, material property constraints, design tolerance etc affecting the serial link performance has been optimized using Taguchi method based on statistical co-analysis. Using the Taguchi statistical techniques, sensitivity analysis on parameter variations affecting HSLINK performance is analyzed and optimized for desired performance.

Circuit modeling of power/ground plane structures for printed circuit boards

Abstract: With the increase of operating frequency and circuit-component density, signal/power integrity issues due to ground bounces become more important for high-speed digital systems. This paper presents a modal analysis resulting in a multiport equivalent circuit model for the power/ground plane structures in printed circuit boards including effects of dielectric, conductor, and radiation losses. Numerical results represented in Z-parameters verified by the measured data are shown to validate the proposed approach. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 47: 97–99, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21092

Comparative Study Of 3D Package Configurations In Power Delivery And Thermal Perspective

Abstract: The advanced packaging technologies including POP (package on package), SIP (system in package), embedded substrate, WLP (wafer-level package) and FO (fan-out) package have been utilized to achieve the small form-factor, high density, and high performance SOC package for mobile hand-held device. [1, 2] As the clock frequency of computation-intensive cores including CPU, GPU, and NPU increases, the impact of power delivery and temperature control of 3D package on the upper limit of performance becomes bigger and bigger. In this paper, several packaging configurations integrating high bandwidth and density DRAM and high performance SOC will be compared in terms of power delivery and thermal dissipation. POP and two kinds of SIP will be analyzed. POP has been popular packaging structure used for smart phone application, which has given small form-factor with high bandwidth DRAM package over SOC package. Although the flexibility and scalability provided by POP has been attractive in mobile terminal, SIP is being considered to maximize the performance of SOC within limited form-factor in hand-held device. Two kinds of SIP including side-by-side SIP and stacked SIP will be determined. While side-by-side SIP configuration is constructed by stacked SOC dies and stacked DRAM dies which are placed side-by-side, stacked SIP configuration is constructed by stacked DRAM dies on SOC dies which are interconnected by TSV (through silicon via). While side-by-side SIP configuration is more attractive than other configurations in thermal-perspective with several conditions, stacked SIP configuration has more advantage in terms of power delivery. Based on the power delivery network impedance and thermal violation region graph given by thermal resistance matrix [11], the comprehensive analysis including power integrity and thermal characterization will be presented with several POP and SIP configuration.

Latency Insertion Method (LIM) for Electro-Thermal Analysis of 3-D Integrated Systems at Pre-Layout Design Stages

Abstract: In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. Application of the method to the problems specific to the early pre-layout design stages is considered. This method can be particularly useful for the early tradeoff and feasibility studies of on-chip and off-chip interconnect systems as well as of entire chip and package structures. The proposed method is shown to be suitable for modeling of both electrical and thermal phenomena occurring in high-speed high-performance very large scale integration circuits at the pre-layout design stages. Capability of the LIM to perform steady state and transient thermal analysis of a 3-D integrated circuit model is demonstrated with an example derived from an actual industry design. The experiments carried out in this paper demonstrate that the proposed methodology significantly outperforms conventional computer-aided design tools.

Antenna environment sensing device

Abstract: Embodiments relate to a sensing device configured to sense the environment of an antenna in a wireless communications or wireless power transfer device without impacting data signal or transferred power integrity. By incorporating a sensing device in the wireless device that operates outside the data signal operating and operational power transfer frequency(s) of the antenna, send/receive data signal integrity may be retained while sensing the environment of the antenna. The sensing device may further use properties of the sensed environment to adjust the configuration of a tunable antenna to decrease signal degradation due to the environment and increase battery life or power transfer efficiency of the wireless device.