Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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09 Oct 2009
TL;DR: In this paper, the suppression of unwanted noise in high speed power buses by the adoption of Photonic Crystal Power/Ground Layer (PCPL) structure is investigated in terms of S-parameters and Electric field distribution.
Abstract: This paper investigates the suppression of unwanted noise in high speed power buses by the adoption of Photonic Crystal Power/Ground Layer (PCPL) structure. The performance of PCPL with different densities of high dielectric rods is analyzed in terms of S-parameters and Electric field distribution. An attempt is made in order to relate geometrical properties (like rods' density and filling ratio) to the shift of the central frequency of the band gaps a well as bandwidth. The simulated results are validated by means of comparison with measured data.
6 citations
01 Oct 2013
TL;DR: Power integrity has become a major integration challenge even for low power ARM-based SoC design and some important aspects for SoC chip design are described.
Abstract: Summary form only given. Power integrity has become a major integration challenge even for low power ARM-based SoC design. As performance requirements demand higher speed, more advanced process nodes reduce transistor level voltage margin, and low power consumption dictate aggressive power saving schemes such as more frequent power mode shifts and power gating, it's challenging to satisfy the power integrity requirements. Following descriptions are some important aspects for SoC chip design.
6 citations
03 Apr 2013
TL;DR: Simulation based on ICEM modeling modified by an empirical coefficient in order to take into account the circuit aging is proposed to model the evolution of the power integrity induced by device aging.
Abstract: Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity of digital integrated circuits and clarifying its origin. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip are combined with electric stress to characterize the influence of aging on power integrity. Simulation based on ICEM modeling modified by an empirical coefficient in order to take into account the circuit aging is proposed to model the evolution of the power integrity induced by device aging.
6 citations
TL;DR: Simulations based on ICEM modeling modified by an empirical coefficient to model the evolution of the emission induced by device aging is proposed and tested and tested.
Abstract: Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity and the conducted emission of digital integrated circuits, clarifying the origin of electromagnetic emission evolution and proposing a methodology to predict this evolution. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip and conducted emission measurements are combined with electric stress to characterize the influence of aging. Simulations based on ICEM modeling modified by an empirical coefficient to model the evolution of the emission induced by device aging is proposed and tested.
6 citations
TL;DR: In this article, the reduction design technique of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance was introduced, the resonance frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor.
Abstract: This paper introduces the reduction design technique of the resonance phenomenon of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance. With the technique, the resonant frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor. From the simulation result, it was confirmed that the PCB's resonance phenomenon reduction design technique should have the reduction effect in the inner motherboard of the industrial controller. This research will be contributed to the improvement of the safety of a PDN (Power Delivery Network) structure in the layout design technique of the PCB.
6 citations