Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Enhancing system-wide power integrity in 3D ICs with power gating

Abstract: Power gating is a commonly used method to reduce subthreshold leakage current in nanoscale technologies. In through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs), power gating can significantly degrade system-wide power integrity since the decoupling capacitance associated with the power gated block/plane becomes ineffective for neighboring active planes, as demonstrated in this paper. A reconfig-urable decoupling capacitor topology is investigated to alleviate this issue by exploiting the ability of via-last TSVs to bypass plane-level power networks when delivering the supply voltage. Reconfigurable decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, thereby significantly reducing both RMS power supply noise (by up to 46%) and RMS power gating (in-rush current) noise (by up to 85%) at the expense of a slight increase in area (by 1.55%) and peak power consumption (by 1.36%).

Static and quasi-dynamic load balancing in parallel FDTD codes for signal integrity, power integrity, and packaging applications

Abstract: The finite-difference time-domain (FDTD) method is a robust technique for calculating electromagnetic fields, but practical problems, involving complex or large geometries, can require a long time to calculate on any one single-processor computer. One computer with many processors or many single-processor computers can reduce the computation time. However, some FDTD cell types, e.g., PML cells, require more computation time than others. Thus, the size and shape of the individual process allocations can significantly influence the computation time. This paper addresses these load balancing issues with static and quasi-dynamic approaches. The message-passing interface (MPI) library is applied to a three-dimensional (3D) FDTD code. Timing results including speedup and efficiency, are presented for trials run on a cluster of sixteen processing nodes and one server node. Two examples are shown in this paper, a power bus with 16 decoupling capacitors and a five layer power distribution network. In such models, the problem size and complexity make modeling with a serial code impractical and time consuming for engineering. Models with several million cells take days to run, but proper implementation, including load balancing, can reduce this execution time to hours on a sufficiently powerful cluster.

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP

Abstract: Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last assembly manufacturing availability. To date, the laminate-substrate based interposer-PoP has been employed for high-end mobile APs with very high-volume production. Recently, this interposer-PoP design has faced some technical limitations including the need to reduce: top and bottom routing layer thickness, copper (Cu) trace line/space and via size for next generation mobile APs. These reductions may require ultra-thin package z-height and high-bandwidth bottom and top routing layers. To address these challenges, a new interposer-PoP with High-Density Fan-Out (HDFO) redistribution layer (RDL) routing layer has been designed and demonstrated. It is part of an initiative to achieve an ultra-thin package z-height, interposer-PoP structure with high bandwidth and improved signal integrity/power integrity (SI/PI) routing layer using a chip-last assembly manufacturing process flow. This paper will discuss package-level characterizations on the interposer-PoP with HDFO RDL routing layer as well as package z-height evaluation, temperature-dependent package warpage measurements and package-level reliability tests conducted in accordance with JEDEC.

Mobile AP GPU power distribution network simulation and analysis based on chip power model

Abstract: These days, mobile devices require low-power consumption. To meet these requirements, IC's operating voltage is continuously lowered. As a result, power noise margin decreases which require more precise Power Distribution Network (PDN) design. In this work, we simulated and analyzed the mobile Application Processor (AP) GPU system based on Chip Power Model (CPM). We applied GPU's current model to simulate simultaneous switching noise and power noise in the chip PDN. To verify the model and simulation set-up, we measured voltage ripple and compared with simulation. We concluded that our simulation setup is reliable and conducted power integrity case studies for the future PDN design.

Nonorthogonal 2.5-D PEEC for Power Integrity Analysis of Package-Board Geometries

Abstract: Design of the power ground layout of a multilayered printed circuit board (PCB) is crucial for low noise and stable power supply. 2.5-D tools are better suited for early stage power distribution network (PDN) analysis over 3-D full-wave electromagnetic solvers due to faster simulation times. For example, the multilayered finite difference method (MFDM), which is based on a 2.5-D formulation on an orthogonal mesh grid, can accurately model and analyze power planes. However, this method loses its advantage while analyzing planes with irregular shapes and holes, which require unnecessarily fine discretization at boundaries for a suitable staircase approximation in an orthogonal grid. In this paper, a nonorthogonal 2.5-D partial element equivalent circuit (PEEC) formulation is proposed, employing quadrilateral mesh elements for efficient simulation of the PDN. The individual stamps for resistance, inductance, capacitance, and conductance elements for a unit quadrilateral cell are derived. Further, the methodology is enhanced to capture coplanar coupling through the introduction of mutual inductance and capacitive terms between neighboring PEEC cell pairs. The numerical results demonstrate good accuracy compared with a 3-D full-wave commercial tool for layered PCB geometries. The efficiency of the proposed method is benchmarked against an orthogonal MFDM implementation and a commercial 2.5-D tool.