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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


Papers
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Patent
20 Jul 2011
TL;DR: In this paper, a novel ultra wide band electromagnetic band gap structure which belongs to the technical field of information is presented, which is mainly used for replacing a power layer of the traditional high speed circuit/microwave circuit so as to suppress ground bounce noise in the structures and realize better power integrity.
Abstract: The invention provides a novel ultra wide band electromagnetic band gap structure which belongs to the technical field of information. The structure is mainly used for replacing a power layer of the traditional high speed circuit/microwave circuit so as to suppress ground bounce noise in the structures and realize better power integrity. The structure has a typical three-layer circuit board structure comprising a dielectric layer in the middle and two metal layers up and down, wherein the electromagnetic band gap structure is arranged on the upper layer. In the invention, a typical example is verified, i.e. a sample prepared in an experiment is tested through a network analyzer, which confirms that the structure provided by the invention can realize noise suppression superior to -30dB to any two ports in a frequency range from 500MHz to 5.5GHz.

5 citations

Journal ArticleDOI
TL;DR: Fundamental issues of early-stage power grid design from architecture to layout are tackled, including extraction, modeling, and optimization, for sub-32nm chips, which may have more significant impact than expected on power integrity.
Abstract: Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early stage when the design database is not complete, including extraction, modeling, and optimization. This article tackles these fundamental issues of early-stage power grid design from architecture to layout. The proposed methods have been silicon validated on 32nm on-market chips and successfully applied to a 22nm design for its early-stage power grid design. The findings from such practices reveal that, for sub-32nm chips, an intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and needs to be well addressed at early stage.

5 citations

Journal ArticleDOI
TL;DR: An EBG structure for power distribution network is optimized with the presented GA method to improve the performances of power integrity and agreements between the measured results and the simulation ones are observed.
Abstract: In this paper, an improved genetic algorithm (GA) for automatically optimizing electromagnetic bandgap (EBG) structure with good power integrity performance is presented. The traditional GA is improved in several ways including Hamming Distance initialization, elite selection and non-repeating crossover, which can generate initial population charactering solution space in detail, increase crossover efficiency, and accelerate convergence. Furthermore, an EBG structure for power distribution network is optimized with the presented GA method to improve the performances of power integrity. The simultaneous switching noise propagation can be prohibited from 0.38 GHz to 20 GHz with a suppression level of -60 dB. Good agreements between the measured results and the simulation ones are observed.

5 citations

Proceedings ArticleDOI
08 Mar 2010
TL;DR: Using the proposed method, multiple stacked power/ground plane pairs having holes and apertures can be modeled as an equivalent circuit suitable for the Latency Insertion Method (LIM), which is one of the fast transient simulation methods based on the “leapfrog” algorithm.
Abstract: This paper presents a modeling method for power distribution networks (PDNs) consisting of multilayered power/ground planes of the PCB/Package. Using our proposed method, multiple stacked power/ground plane pairs having holes and apertures can be modeled as an equivalent circuit. The structure of this equivalent circuit is suitable for the Latency Insertion Method (LIM), which is one of the fast transient simulation methods based on the "leapfrog" algorithm. Numerical results show that the leapfrog algorithm enables a speed-up of 105 and 486 times compared to the linear circuit simulator based on the sparse LU-decomposition and HSPICE, respectively, with the same level of accuracy.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852