Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Fundamentals of Power Integrity

Abstract: •Industry trend and power integrity challenges •Capacitor •Power impedance measurement •Power decoupling strategy •Target impedance •On-die power integrity analysis •Package-level power integrity analysis •Die/Package/Board co-design methodology •SSO and SSI •Open topics and Q&A

Framework for co-simulation of signal and power integrity in server systems

Abstract: Considerations for comprehensive simulation and analysis of high-speed links in complex server systems are discussed in this work. A framework that considers the interactions between multiple signals and the power distribution network is described. In the last section, the nature of the interactions between power and signal domains is analyzed by means of a simplified scenario at board level.

Application of Integral Analysis Technique to Determine Signal- and Power Integrity of Advanced Packages

Abstract: In this paper an application of an integral analysis technique is demonstrated for determining signal integrity (SI) and power integrity (PI) of complex and advanced package solutions. A representative system-in-package (SiP) product has been selected as a carrier for our study, which is focused on analysis methodology, tools and flow. In particular, possibility to easily support what-if simulations for SI and PI, including analysis with distributed on-chip decoupling capacitors is investigated and highlighted. Importance of balancing between accuracy, CPU time and ease-of-use is also underlined.

Power Integrity Analysis For Jitter Characterization

Abstract: Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC and increase in the operating frequencies has immensely changed the classical understanding of noise in the new age complex ICs. Switching noise specifically has become a dominating criteria for high performance digital and mixed signal ICs. Voltage variations on the power/ground nodes of a circuit is a type of switching noise affecting digital and mixed-signal ICs. Therefore, power integrity (PI) has become a critical challenge that must be addressed at the system level considering the parasitic effects of package and board. In this work, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow. This methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This approach has been successfully exploited to guarantee the power integrity on an industrial design. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins.

Enabling fast power integrity transient analysis through parameterized small-signal macromodels

Abstract: In this paper, we present an automated strategy for extracting behavioral small-signal macromodels of biased nonlinear circuit blocks. We discuss in detail the case study of a Low DropOut (LDO) voltage regulator, which is an essential part of the power distribution network in electronic systems. We derive a compact yet accurate surrogate model of the LDO, which enables fast transient power integrity simulations, including all parasitics due to the specific layout of the LDO realization. The model is parameterized through its DC input voltage and its output current and is thus available as a SPICE netlist. Numerical experiments show that a speedup up to 700X is achieved when replacing the extracted post-layout netlist with the surrogate model, with practically no loss in accuracy.