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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Journal ArticleDOI
TL;DR: In this article, the problem of noise sensor placement along with a novel sensing quality metric is formulated and an efficient algorithm is proposed to solve it, which is proven to attain the best result in the class of polynomial complexity approximations.
Abstract: Runtime noise management systems can enforce power integrity without significantly increasing design margins. These systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold voltage for these sensors. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric to be maximized. We then put forward an efficient algorithm to solve it, which is proven to attain the best result in the class of polynomial complexity approximations. We further solve the problem to minimize the system failure rate subject to a given runtime performance loss (RPL) constraint. Experimental results on a set of industrial power grid designs show that, compared to a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aimed at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x, and 6.2x, respectively. The trade-off between the system failure rate and the RPL is also presented. To the best of the authors' knowledge, this is the very first in-depth work on noise sensor deployment.

4 citations

Proceedings ArticleDOI
01 Jun 2014
TL;DR: This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming.
Abstract: Power Integrity is maintained in a high speed system by designing an efficient decoupling network This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming A real-world example is presented for the same The minimum number of capacitors that could achieve the target impedance over the desired frequency range are found along with their optimal locations In order to solve an industrial problem, the s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM

4 citations

Proceedings ArticleDOI
22 May 2018
TL;DR: How the package behavior can change depending on the interaction with PCB parameters is shown, and a methodology to optimize on-package decoupling taking into account the system variability is proposed.
Abstract: A key aspect of power integrity in modern electronic systems is the choice and optimization of decoupling capacitors. Traditionally, this issue has been addressed at PCB level, but the integration of discrete SMD capacitors inside BGA package substrates is becoming more and more common in complex high-speed digital devices. In the context of semiconductors industry, the on-package decoupling applied to digital microcontrollers needs to be defined, often without any clear information on system configuration. This paper shows how the package behavior can change depending on the interaction with PCB parameters, and proposes a methodology to optimize on-package decoupling taking into account the system variability.

4 citations

Proceedings ArticleDOI
21 Nov 2007
TL;DR: The reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform is verified to be accurate in HSPICE simulation and the precision and reproducibility of high speed current profile, icc(t) is discussed by using this reverse engineering technique.
Abstract: Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.

4 citations

Proceedings ArticleDOI
15 Mar 2015
TL;DR: In this article, a modulated CPM (MCPM) design and signoff process for power distribution network (PDN) is described, where the chip gate level simulation is performed over an extended period of time to generate the value change dump plus (VPD) file, with realistic low to mid frequency current components.
Abstract: As the semiconductor industry advances to ever smaller technology nodes, the power distribution network (PDN) is becoming an essential design factor to ensure system performance and reliability [1]. The time domain simulations typically utilize the chip power model (CPM), generated by Ansys RedHawk, as the current load. The typical CPM only includes current consumption in a few clock cycles, which includes the high frequencies components (several hundreds of MHz), but losing mid to low frequencies. This paper describes a modulated CPM (MCPM) design and signoff process for PDN. The first step is frequency domain analysis of PDN to identify the die-package resonance frequency. Then the chip gate level simulation is performed over an extended period of time to generate the VPD (Value Change Dump plus) file, with realistic low to mid frequency current components. This information is then used to modulate the CPM as the current load for the system level time domain noise simulations. This PI analysis flow was validated using a set of three test cases, with reasonable simulation-measurement correlation achieved. This analysis flow enables more effective power/ground plane layout optimization and capacitor optimization in a timely manner.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852