Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

Abstract: The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and temperature (PVT) variations in sub-nanometer DRAM process are required to improve performance. To achieve 24Gb/s/pin on a 1.35V DRAM process, this work proposes a GDDR6 DRAM with a half-rate clocking architecture and optimized I/O.

On-chip decouplig capacitor preplacement for power integrity enhancement

Abstract: With the rapid technology scaling, logic devices are more susceptible to power distribution network (PDN) power noise. To relieve power noise, traditionally the gate capacitance of transistor is used for on-chip decoupling capacitor (decap). In this paper, we investigate the power integrity characteristics of on-chip decap, such as power noise and current consumption, and propose the decap preplacement flow to relieve them. Compared to the non-preplacement approach, experimental results show the worst instantaneous voltage drop(IVD) can be reduced by about 7.16% and average supply current can be reduced by 3.05% by using preplacement scheme.

Reducing SoC electromagnetic emissions by design

Abstract: This paper deals with the design of power supply distribution network in CMOS System-on-Chips to reduce electromagnetic emissions. The main sources of both conducted and radiated emissions are pointed out and the most popular solutions for these problems are summarized. Based on that, the paper shows a new power supply network and grounding scheme that strongly mitigate the off-chip propagation of core circuit interference that gives rise to electromagnetic emissions. The proposed power supply circuit can be implemented as a simple redesign of conventional power supply circuit without any modification to the logic design flow.

Power Integrity Comparison of Off-chip, On-interposer, On-chip Voltage Regulators in 2.5D/3D ICs

Abstract: Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

Signal and power integrity (SI/PI) analysis of heterogeneous integration using embedded multi-die interconnect bridge (EMIB) technology for high bandwidth memory (HBM)

Abstract: Silicon interposer with high bandwidth memory (HBM) has been developed to achieve a terabyte/s bandwidth graphic card module. However, silicon interposer still has critical drawbacks regarding the complexity of fabrication and manufacturing cost. Especially, expensive through-silicon-via (TSV) process has become a serious problem for cost reduction. An innovative package substrate called embedded multi-die interconnect bridge (EMIB) becomes alternative solution for memory industries to reduce manufacturing cost and complexity of fabrication process of silicon interposer. Consequently, signal and power integrity (SI/PI) design and analysis of silicon based EMIB package substrate becomes essential, because it will be dominantly affected to HBM interface. In this paper, superior SI designs of EMIB is proposed and analyzed considering manufacturing cost. In addition, the impact on hierarchical PDN impedance due to EMIB is discussed and we proposed further direction for PI improvement. Proposed designs and analysis of EMIB package substrate are expected to be widely adopted in memory industries for next generation HBM interface.